Abstract
This paper proposes 2 × unrolled high-speed architectures of the MISTY1 block cipher for wireless applications including sensor networks and image encryption. Design space exploration is carried out for 8-round MISTY1 utilizing dual-edge trigger (DET) and single-edge trigger (SET) pipelines to analyze the tradeoff w.r.t. speed/area. The design is primarily based on the optimized implementation of lookup tables (LUTs) for MISTY1 and its core transformation functions. The LUTs are designed by logically formulating S9/S7 s-boxes and FI and {FO + 32-bit XOR} functions with the fine placement of pipelines. Highly efficient and high-speed MISTY1 architectures are thus obtained and implemented on the field-programmable gate array (FPGA), Virtex-7, XC7VX690T. The high-speed/very high-speed MISTY1 architectures acquire throughput values of 25.2/43 Gbps covering an area of 1331/1509 CLB slices, respectively. The proposed MISTY1 architecture outperforms all previous MISTY1 implementations indicating high speed with low area achieving high efficiency value. The proposed architecture had higher efficiency values than the existing AES and Camellia architectures. This signifies the optimizations made for proposed high-speed MISTY1 architectures.
Highlights
With the advances in high-speed wireless applications, the quest to provide secure transfer of data has been of major concern [1, 2]. e efforts are underway to provide a realtime encryption solution for high data transmissions with minimum overhead in terms of power [3,4,5]. is study primarily focuses on high-speed implementations of a 64 bit MISTY1 block cipher for a wide range of applications, i.e., wireless networks, Ethernet devices, image encryption, and radio network controllers (RNCs) [6]
MISTY1 block cipher. e hardware architecture of MISTY1 and its major subfunctions FO and FI constitute a repetitive loop structure [11]. erefore, the MISTY1 algorithm is suitable for the implementations of resource-constrained and high-speed applications
Hardware Implementation Results and Comparison e proposed MISTY1 high-speed architectures are implemented on field-programmable gate array (FPGA) Xilinx Virtex-7, XC7VX690T
Summary
With the advances in high-speed wireless applications, the quest to provide secure transfer of data has been of major concern [1, 2]. e efforts are underway to provide a realtime encryption solution for high data transmissions with minimum overhead in terms of power [3,4,5]. is study primarily focuses on high-speed implementations of a 64 bit MISTY1 block cipher for a wide range of applications, i.e., wireless networks, Ethernet devices, image encryption, and radio network controllers (RNCs) [6]. 2 × area-efficient MISTY1 design schemes are proposed in [17] based on the combined substitution unit and threshold throughput requirements. Contrary to low-area cryptographic hardware architectures, high-speed encryption algorithms utilize LUTs/RAMs or optimized combinational logic for s-boxes using pipelined schemes [20,21,22,23,24,25]. Owing to high-speed and efficient implementation requirements, the architecture presented in [20] utilizes FPGA RAM blocks for the implementation of S7/S9 s-boxes. E unique contributions of the proposed MISTY1 n 8-round pipelined architectures are as follows: Optimized implementation of MISTY1 S9/S7 s-boxes and transformation functions, i.e., FL, FI, FO, and 32bit XOR, by logic formulation of 4, 5, and 6 bit input LUTs for area reduction.
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