High-performance Thin-film Transistors Research Articles

Ultranarrow Bandgap Naphthalenediimide-Dialkylbifuran-Based Copolymers with High-Performance Organic Thin-Film Transistors and All-Polymer Solar Cells.

A new polymer acceptor poly{(N,N'-bis(2-ethylhexyl)-1,4,5,8-naphthalenedicarboximide-2,6-diyl)-alt-5,5-(3,3'-didodecyl-2,2'-bifuran)} (NDI-BFR) made from naphthalenediimide (NDI) and furan-derived head-to-head-linked 3,3'-dialkyl-2,2'-bifuran (BFR) units is reported in this study. Compared to the benchmark polymer poly(naphthalenediimide-alt-bithiophene) (N2200), NDI-BFR exhibits a larger bathochromic shift of absorption maxima (842 nm) with a much higher absorption coefficient (7.2 × 104 m-1 cm-1 ), leading to an ultranarrow optical bandgap of 1.26 eV. Such properties ensure good harvesting of solar light from visible to the near-infrared region in solar cells. Density functional theory calculation reveals that the polymer acceptor NDI-BFR possesses a higher degree of backbone planarity versus the polymer N2200. The polymer NDI-BFR exhibits a decent electron mobility of 0.45 cm2 V-1 s-1 in organic thin-film transistors (OTFTs), and NDI-BFR-based all-polymer solar cells (all-PSCs) achieve a power conversion efficiency (PCE) of 4.39% with a very small energy loss of 0.45 eV by using the environmentally friendly solvent 1,2,4-trimethylbenzene. These results demonstrate that incorporating head-to-head-linked BFR units in the polymer backbone can lead to increased planarity of the polymer backbone, reduced optical bandgap, and improved light absorbing. The study offers useful guidelines for constructing n-type polymers with narrow optical bandgaps.

Catalytic Metal-Accelerated Crystallization of High-Performance Solution-Processed Earth-Abundant Metal Oxide Semiconductors.

As an alternative strategy for conventional high-temperature crystallization of metal oxide (MO) channel layers, the catalytic metal-accelerated crystallization (CMAC) process using a metal seed layer is demonstrated for low-temperature crystallization of solution-processed MO semiconductors. In the CMAC process, the catalytic metal layer plays the role of seed sites for initiating and accelerating the crystallization of amorphous MO films. Generally, the solution-processed crystalline-TiO2 (c-TiO2) films required high-temperature crystallization conditions (≥500-600 °C), showing low electrical performance with a high defect density. In contrast, the suggested CMAC process could effectively lower crystallization temperature of the a-TiO2 films, enabling high-quality c-TiO2 films with well-aligned anatase grains and low-defect density. The various crystalline catalytic layers were deposited over the earth-abundant n-type amorphous titanium oxide (a-TiO2) films. Also, then, the CMAC process was performed for facile low-temperature translation of solution-processed a-TiO2 to a highly crystallized state. In particular, the Al-CMAC process using the crystalline thin-aluminum (Al) catalytic metal seed layer facilitates low-temperature (≥300 °C) crystallization of the solution-processed a-TiO2 films and the fabrication of high-performance solution-processed c-TiO2 thin-film transistors with superior field-effect mobility, good on/off switching behavior, and improved operational stability.

Enhancement-/Depletion-Mode TiO2 Thin-Film Transistors via O2/N2 Preannealing

Metal-oxide thin-film transistors (TFTs) promise to enable lightweight and low-power applications, such as ultrathin active matrix displays and low-cost RF identification tags. However, most reported high-performance metal-oxide TFTs contain high-cost indium and gallium elements, leading to constraints in cost-sensitive application. Herein, we present enhancement-/depletion-mode (E-/D-mode) TiO2 TFTs via $\text{O}_{{2}}/\text{N}_{{2}}$ preannealing of TiO2 channel material prior to device fabrication process. It is found that the O2-annealed TiO2 TFTs exhibit improved performances compared to N2-annealed TiO2 TFTs, including increased mobility ( $\mu $ ), higher ON-/OFF-current ratio (ION/IOFF), and lower subthreshold swing (SS). This can be attributed to the passivation effects of O2 annealing, which leads to less oxygen vacancies at the channel and channel/oxide interface. On the other hand, the ionized oxygen vacancies result in the increased electron concentration in N2-annealed films and, thus, the negative shift of ${V}_{\text {th}}$ in the TFT performance. This article delivers a possible approach to improve oxide TFT performance by passivation of oxygen vacancies. Furthermore, the controlled annealing process has a great potential in the logic inverter applications when both E- and D-mode TFTs are implemented.

Wettability Control of Interfaces for High-Performance Organic Thin-Film Transistors by Soluble Insulating Polymer Films.

Organic small-molecule semiconductors have higher carrier mobility compared to polymer semiconductors, while the actual performances of these materials are susceptible to morphological defects and misalignment of crystalline grains. Here, a new strategy is explored to control the crystallization and morphologies of a solution-processed organic small-molecule semiconductor 2,7-dioctyl[1]benzothieno[3,2-b][1]benzothiophene (C8-BTBT) using soluble polymer films to control the wettability of substrates. Different from the traditional surface modification method, the polymer layer as a modification layer is soluble in the semiconductor solution during the fabrication of organic thin-film transistors (OTFTs). The dissolved polymer alters the state of the semiconductor solution, which in turn, changes the crystallographic morphologies of the semiconductor films. By controlling the solubility and thickness of the polymer modification layers, it is possible to regulate the grain boundary and domain size of C8-BTBT films, which determine the performances of OTFTs. The bottom-gate transistors modified by a thick PS layer exhibit a mobility of >7 cm2/V·s and an on/off ratio of >107. It is expected that this new modification method will be applicable to high-performance OTFTs based on other small molecular semiconductors and dielectrics.

Highly efficient UV-Ozone treatment for IAZO active layer to facilitate the low temperature fabrication of high performance thin film transistors

We had found for the first time that short-time UV-ozone treatment can effectively regulate the electrical properties of sputtered InAlZnO (IAZO) films, and we successfully prepared high performance IAZO thin film transistors (TFTs) without thermal annealing. After the UV-ozone treatment, all IAZO films exhibited very flat surface topographies with small root mean square roughnesses (0.167–0.195 nm). With the increase of UV-ozone treatment time, the oxygen vacancies and consequently the carrier concentration of the films decreased monotonically, while the highest Hall mobility of 29.4 cm2/V was obtained for the 5 min-treated film. The IAZO TFT with 5 min UV-ozone treatment exhibited the best overall electrical properties with a high saturation mobility of 8.76 cm2/V, a high on-off current ratio of 6.44 × 108 and a low subthreshold swing of 0.73 V/dec. Meanwhile, it also displayed good negative bias illumination stability with a small shift of −0.51 V observed in threshold voltage after the device being stressed for 3000 s.

Solution-processed ITO thin-film transistors with doping of gallium oxide show high on-off ratios and work at 1 mV drain voltage

Indium tin oxide (ITO) is generally used as an electrode material but has recently been demonstrated to be a competitive candidate for use in semiconductor layers in high-performance thin-film transistors (TFTs), due to its high mobility and strong resistance to wet-etching. Here, we demonstrate TFTs using solution-processed, ultra-thin ITO films with outstanding switching performance. These devices exhibit a mobility of up to 15 cm2 V−1 s−1 and a high on-off ratio of 108. Because the device exhibits significant instability under stress tests, moderate doping with Ga as a dopant is introduced to form Ga-doped ITO TFTs. The resulting device has much enhanced stability, near-zero turn-on voltage, and a high on-off current ratio of 108. Through further involvement of an AlOx dielectric layer, the Ga-doped ITO TFTs exhibit a high apparent mobility of more than 40 cm2 V−1 s−1 and operate at small gate voltages (3 V). Remarkably, the device maintains an on-off ratio of over 104 at drain voltages as small as 1 mV.

Hydrogen-Defect Termination in SnO for p-Channel TFTs

Developing high-performance p-channel oxide thin-film transistor (TFT) and practical oxide TFT-based complementary circuits is the most persistent challenge for oxide electronics and a major hurdle...

Low-Voltage IGZO TFTs Using Solution-Deposited OTS-Modified Ta2O5 Dielectric

Low-voltage, high-performance thin film transistors (TFTs) that use amorphous metal oxide (MO) semiconductors as the active layer have been getting tremendous attention due to their essential role in future portable electronic devices and systems. However, reducing the operating voltage of these devices to or below 1 V is a very challenging task because it is very difficult to obtain low threshold voltage ( ${V}_{\text {TH}}$ ) and small subthreshold swing (SS) MO TFTs. In this article, indium gallium zinc oxide (IGZO) TFTs that use solution-deposited Ta2O5 operating at 1 V are demonstrated. To enhance the dielectric properties of the fabricated ultrathin ( ${d} \sim {22}$ nm $\pm ~2$ nm) tantalum pentoxide films, ${n}$ -octadecyltrichlorosilane (OTS) self-assembled monolayer (SAM) was used. The morphology and electrical properties of both pristine and OTS-treated Ta2O5 films have been studied. The optimized Ta2O5/OTS IGZO TFTs operate at 1 V with saturation field-effect mobility larger than 2.3 cm2/ $\text{V}\cdot \text{s}$ , threshold voltage of around 400 mV, SSs below 90 mV/dec, and current ON- OFF ratios well above $10^{{5}}$ . The performance of the presented TFTs is high enough for many commercial applications such as disposable sensors or throwaway, low-end electronics significantly reducing the cost of their production.

Understanding the Role of Temperature and Drain Current Stress in InSnZnO TFTs with Various Active Layer Thicknesses.

Thin-film transistor (TFT) devices composed of metal oxide semiconductors have attracted tremendous research attention globally in recent years. Owing to their ability to offer mobility, metal oxide semiconductor materials can enable high-performance TFTs for next-generation integrated display devices. Nevertheless, further breakthroughs of metal oxide TFTs are mainly obstructed by their long-term variability, the reason for which is not yet fully understood. Herein, TFTs based on InSnZnO (ITZO) with various thicknesses (TITZO) were prepared and their long-term stabilities under test temperatures and drain current stress were investigated. The results indicate that ITZO TFTs exhibit outstanding electrical properties regardless of the TITZO, including a high saturated mobility of over 35 cm2V−1s−1 and sharp subthreshold swing. Note that the transfer and output characteristic curves of the device with a thick TITZO of 100 nm express an abnormal current surge when high gate and drain voltages are exerted, which is attributed to the floating body effect, caused when the imposed electric field induces impact ionization near the drain side. More interestingly, these drain current stress results further suggest that the abnormal shift behavior of the electrical properties of the ITZO TFTs with a TITZO of greater than 75 nm is observed to deteriorate gradually with increasing temperature and drain current bias. This study addresses that such a degradation effect should be restrained for the operation of high-mobility devices.

Aqueous Solution-Processed Boron-Doped Gallium Oxide Dielectrics for High-Performance Thin-Film Transistors

In this paper, we report aqueous solution-processed boron-doped gallium oxide dielectric thin films for high-performance oxide thin-film transistors. The role of B incorporation on the microstructu...

Achieving high performance thin film transistors based on gallium doped indium zinc tin oxide

Abstract In this paper, staggered bottom-gate amorphous oxide thin film transistors with a channel layer of gallium doped indium-zinc-tin oxide (IZTO:Ga) have been fabricated by radio frequency magnetron sputtering at room temperature on SiO2/Si substrate. Under the annealing treatment at 350 °C in air atmosphere, the IZTO:Ga films still kept amorphous and the transmittivity of the IZTO:Ga film was over 80% in the visible range. The IZTO:Ga TFTs showed desired performance with saturation mobility of 36.3 cm2V−1s−1, subthreshold swing value of 0.42 V/decade, current on/off (Ion/Ioff) up to 109 with the off current as low as 4.5 × 10−13 A and exhibited the enhancement mode with a threshold voltage of 1.0 V. Besides, the positive and negative bias stability of the IZTO:Ga TFTs without passivation is also measured in air with the stress time up to 3600 s and the threshold voltage (VTH) showed a shift for +4.6 V and −5.4 V respectively.

Interface Engineering With Polystyrene for High-Performance, Low-Voltage Driven Organic Thin Film Transistor

We report a solution-processed, high-performance organic thin-film transistor (OTFT), using polystyrene (PS) as interlayer with the semiconducting material P2TDPP2TFT4 as an active layer. We achieved a significant improvement employing the PS as an interlayer between the P2TDPP2TFT4 and ${{{\text {AlO}}}}_{X}$ gate insulator. The filed-effect mobility ( $\mu _{{{\text {FE}}}}$ ) and ON/OFF current ratio ${(}{I}_{{ \mathrm{\scriptscriptstyle ON}}}/{I}_{{ \mathrm{\scriptscriptstyle OFF}}}{)}$ reached to $0.82\,\,{{{\text {cm}}}}^{{{{2}}}}{\cdot } {{\text {V}}}^{{{-{1}}}}{\cdot } {{\text {s}}}^{{{-{1}}}}$ and ~105, respectively, which is higher than the devices fabricated with commonly used self-assembled monolayer (SAM) octadecyltrimethoxysilane (OTS) modified substrate under similar experimental conditions. Further analysis of the modified gate insulator utilizing atomic force microscopy, X-ray diffraction, and contact angle measurement revealed that smoother surface and lower surface energy were achieved by employing PS interlayer, which leads to more compatible surface energy with the semiconductor and interfacial trap passivation. Passivation of interfacial traps and lower surface energy using PS interlayer leads to the highly stable device performance, suggesting its application as a new interlayer with ${{{\text {AlO}}}}_{X}$ gate insulator to improve device performance.

TFT Channel Materials for Display Applications: From Amorphous Silicon to Transition Metal Dichalcogenides.

As the need for super-high-resolution displays with various form factors has increased, it has become necessary to produce high-performance thin-film transistors (TFTs) that enable faster switching and higher current driving of each pixel in the display. Over the past few decades, hydrogenated amorphous silicon (a-Si:H) has been widely utilized as a TFT channel material. More recently, to meet the requirement of new types of displays such as organic light-emitting diode displays, and also to overcome the performance and reliability issues of a-Si:H, low-temperature polycrystalline silicon and amorphous oxide semiconductors have partly replaced a-Si:H channel materials. Basic material properties and device structures of TFTs in commercial displays are explored, and then the potential of atomically thin layered transition metal dichalcogenides as next-generation channel materials is discussed.

A Unique Approach to Generate Self-Aligned T-Gate Transistors in Counter-Doped Poly-Si With High Etching Selectivity and Isotropy

A unique approach for fabricating poly-Si thin-film transistors (TFTs) with self-aligned T-shaped gate (T-gate) structure is reported. A counter-doped poly-Si process comprises an in-situ doped ${n}^{+}$ poly-Si deposition followed by a subsequentshallow implantation of BF $_{{2}}^{+}$ . Both high etching isotropy in ${n}^{+}$ poly-Si and high etching selectivity between ${n}^{+}$ poly-Si and B-doped poly-Si in a Cl2-based plasma process are the key enablers for the fabrication of our T-gate structures. Thanks to good control in the shape and deformation of our T-gate structure, sidewall air-gap spacers in combination with self-aligned Ni silicided gate and source/drain were established. High-performance sub-micron poly-Si TFTs are evidenced by superior transfer characteristics measured on TFTs with effective gate length of $0.15~\mu \text{m}$ . The unique T-gate structure provides an effective way for possible production of poly-Si radio-frequency TFTs viable for emerging new applications.

Improved Electrical Performance of Oxide Transistor Utilizing Gallium Doping Both in Channel and Dielectric Layers

Here, we report a new strategy to fabricate high performance thin-film transistors (TFTs) by doping gallium (Ga) both in channel (In2O3) and dielectric (Al2O3) layers. The influence of Ga doping on the microstructure and surface morphology of In2O3 films, as well as the oxygen defects states and electrical properties of Al2O3 films have been systematically investigated. The results show Ga doping frustrates In2O3 crystallization and flattens film surface. As for Al2O3, Ga doping increase the dielectric constant, reflective index and decrease the leakage current density. Furthermore, metal oxide TFTs were developed when using In2O3:Ga as the channel and Al2O3:Ga as the dielectric layers. The devices show improved electrical performance and enhanced positive and negative bias stress stability than undoped devices.

Defect gradient control in amorphous InGaZnO for high-performance thin-film transistors

The accuracy control of oxygen-correlated defect densities in the lattice of metal oxide semiconductors is one of the remaining issues restricting the performance of metal oxide-based devices and their commercialization process. This study has successfully realized the gradient control of defects in amorphous InGaZnO through various strategies. X-ray photoelectron spectroscopy results reveal that the 350 °C thermal annealing accompanied with 300 °C pre-treatment is more conducive to improve the quality of a-IGZO and suppress the density of oxygen vacancy defects. Correspondingly, the initial electrical properties of a-IGZO thin-film transistor treated by gradient annealing procedures is superior to those of the devices with one-step 350 °C routine annealing or combined with an intermediate N2O plasma treatment. It is demonstrated that the gradient annealing procedures effectively improve the quality of a-IGZO bulk and its adjacent interfaces. More importantly, the notorious instability induced by the negative bias and illumination stress is significantly suppressed.

Controllable doping and passivation of ZnO thin films by surface chemistry modification to design low-cost and high-performance thin film transistors

Solution-processed metal oxide thin-film transistors have become more popular as they can be used to fabricate transparent and flexible electronics at low cost. However, additional and complex processes for trap-site passivation and doping hinder the potential of the low-cost solution process. This study introduces a surface passivation process involving treatment with 3-aminopropyltriethoxysilane (APTES) that can enhance the electrical properties of ZnO sol–gel thin films. Optical, chemical, and structural analyses of ZnO sol–gel thin films revealed that their trap sites were passivated successfully through APTES treatment under basic conditions. Taking advantage of this process, high-mobility and negligible-hysteresis ZnO thin-film transistors were successfully fabricated, showing an Ion/Ioff of 105, hysteresis as low as 1.13 V, and mobility of up to 0.117 cm2/Vs. Furthermore, a characteristic transition of ZnO sol–gel thin films from semiconductive to semimetallic was observed during investigations with various APTES concentrations.

Thin film transistor based on two-dimensional organic-inorganic hybrid perovskite

Despite the fact that three-dimensional organic-inorganic hybrid perovskite is regarded as a promising material in the field of optoelectronics and microelectronics due to its excellent photoelectric properties, however, the instability under the moisture environment and the gate-voltage screening effect associated with ionic transport are still serious, which restricts the development of perovskite devices. Here in this work, the lead iodide perovskite (PEA)<sub>2</sub>(MA)<i><sub>n–</sub></i><sub>1</sub>Pb<sub>n</sub>I<sub>3<i>n</i>+1</sub> series are successfully prepared by one-step solution method, including pure-two-dimensional (pure-2D), quasi-two-dimensional (quasi-2D) and traditional three-dimensional (3D) perovskite materials. The dimension and microstructure of the perovskites are regulated, and the effects of dimensions on the performance of organic-inorganic hybrid perovskite materials are investigated firstly. The crystallization of the 2D perovskites and 3D perovskite films are observed obviously. Moreover, the surface of pure-2D perovskite film with discoid, regular and micron-sized grains is smoother than that of 3D perovskite film. And also, the unapparent grain boundary is exhibited in the quasi-2D perovskites. A uniform perovskite film with full coverage and inconspicuous grain boundaries facilitates the transmission capacity of the charge carriers in the channel layer due to the reduction of defects caused by the grain boundaries. And benefited from the high-quality films with inconspicuous grain boundary as demonstrated, the quasi-2D hybrid perovskite film exhibits a longer carrier lifetime (<i>τ</i><sub>ns</sub>) than traditional 3D MAPbI<sub>3</sub> perovskite film, revealing that the layered 2D structure is more favorable for carrier transport due to the fewer defects in it. In addition, under the condition of the same environment humidity, the 2D perovskite materials show better moisture stability. Then, to investigate the influences of dimensional structure on the perovskite field-effect devices, we fabricate the bottom-gate and top-contact thin film transistors (TFTs) based on the perovskite materials with different dimensions. As a result, the instability and ion migration effect for each of the devices are suppressed effectively due to the distinct 2D layer-structure and quantum confinement effect, which leads the device performance to be further improved. The device based on quasi-2D (<i>n</i> = 6) channel TFT achieves a hole mobility (<i>μ</i><sub>hole</sub>) of 3.9 cm<sup>2</sup>/(V·s), an on-off current ratio of 10<sup>4</sup> and more, and a 1.85V turn-on voltage of 1.85 V. The first application of quasi-2D organic and inorganic hybrid perovskite materials to thin film transistors provides a new idea for preparing the high-performance and stable thin film transistor devices.

Polymer mask-weakening grain-boundary effect: towards high-performance organic thin-film transistors with mobility closing to 20 cm2 V−1 s−1

Polystyrene-based masks are fabricated to produce top-contact high-resolution (5 μm) electrodes. With this mask, the mobility of DPA-based thin-film transistors could reach 19.22 cm2 V−1 s−1, which is a new breakthrough for DPA thin-film transistors.

Narrow bandgap difluorobenzochalcogenadiazole-based polymers for high-performance organic thin-film transistors and polymer solar cells

A series of difluorobenzochalcogenadiazole-bithiophene copolymers are developed for high-performance organic semiconductors.