High-performance Thin-film Transistors Research Articles

Interfacial molecular screening of polyimide dielectric towards high-performance organic field-effect transistors

The compatibility of the gate dielectrics with semiconductors is vital for constructing efficient conducting channel for high charge transport. However, it is still a highly challenging mission to clearly clarify the relationship between the dielectric layers and the chemical structure of semiconductors, especially vacuum-deposited small molecules. Here, interfacial molecular screening of polyimide (Kapton) dielectric in organic field-effect transistors (OFETs) is comprehensively studied. It is found that the semiconducting small molecules with alkyl side chains prefer to form a high-quality charge transport layer on polyimide (PI) dielectrics compared with the molecules without alkyl side chains. On this basis, the fabricated transistors could reach the mobility of 1.2 cm2 V−1 s−1 the molecule with alkyl side chains on bare PI dielectric. What is more, the compatible semiconductor and dielectric would further produce a low activation energy (EA) of 3.01 meV towards efficient charge transport even at low temperature (e.g., 100 K, 0.9 cm2 V−1 s−1). Our research provides a guiding scheme for the construction of high-performance thin-film field-effect transistors based on PI dielectric layer at room and low temperatures.

All-Solution-Driven Thin-Film Transistor With Low Power Dissipation for Logic Electronics and Neuronal Synapse

For the realization of low-power consumption brain-inspired neuromorphic devices which mimic the biological neuronal information processing methodology, the development of transistors capable of synaptic behaviors and neuronal computation has attracted widespread attention. However, ultrathin, solid-state neuromorphic devices with ultralow energy consumption are still in the exploration stage. Herein, based on an all-solution strategy, oxide-based electrical-double-layer (EDL) thin film transistors (TFTs) have been constructed, demonstrating good operational stability and excellent logic operation functions. Motivated by these excellent characteristics, the TFTs devices triggered by electrical pulses can mimic synaptic behaviors, including excitatory postsynaptic current (EPSC) and paired-pulse facilitation (PPF). In addition, response to electrical stimulus, high-pass filtering characteristics, and short-term memory (STM) and long-term memory (LTM) characteristics have been achieved and investigated. These results reported here have demonstrated that all-solution-driven high-performance oxide-based TFTs enable the achievement of logic electronics with low-power consumption and brain-inspired neuromorphic devices.

Cascaded Logic Gates Based on High-Performance Ambipolar Dual-Gate WSe2 Thin Film Transistors.

Ambipolar dual-gate transistors based on low-dimensional materials, such as graphene, carbon nanotubes, black phosphorus, and certain transition metal dichalcogenides (TMDs), enable reconfigurable logic circuits with a suppressed off-state current. These circuits achieve the same logical output as complementary metal-oxide semiconductor (CMOS) with fewer transistors and offer greater flexibility in design. The primary challenge lies in the cascadability and power consumption of these logic gates with static CMOS-like connections. In this article, high-performance ambipolar dual-gate transistors based on tungsten diselenide (WSe2) are fabricated. A high on-off ratio of 108 and 106, a low off-state current of 100 to 300 fA, a negligible hysteresis, and an ideal subthreshold swing of 62 and 63 mV/dec are measured in the p- and n-type transport, respectively. We demonstrate cascadable and cascaded logic gates using ambipolar TMD transistors with minimal static power consumption, including inverters, XOR, NAND, NOR, and buffers made by cascaded inverters. A thorough study of both the control gate and the polarity gate behavior is conducted. The noise margin of the logic gates is measured and analyzed. The large noise margin enables the implementation of VT-drop circuits, a type of logic with reduced transistor number and simplified circuit design. Finally, the speed performance of the VT-drop and other circuits built by dual-gate devices is qualitatively analyzed. This work makes advancements in the field of ambipolar dual-gate TMD transistors, showing their potential for low-power, high-speed, and more flexible logic circuits.

Selectively Nitrogen Doped ALD-IGZO TFTs with Extremely High Mobility and Reliability.

Achieving high mobility and reliability in atomic layer deposition (ALD)-based IGZO thin-film transistors (TFTs) with an amorphous phase is vital for practical applications in relevant fields. Here, we suggest a method to effectively increase stability while maintaining high mobility by employing the selective application of nitrous oxide plasma reactant during plasma-enhanced ALD (PEALD) at 200 °C process temperature. The nitrogen-doping mechanism is highly dependent on the intrinsic carbon impurities or nature of each cation, as demonstrated by a combination of theoretical and experimental research. The Ga2O3 subgap states are especially dependent on plasma reactants. Based on these insights, we can obtain high-performance indium-rich PEALD-IGZO TFTs (threshold voltage: -0.47 V; field-effect mobility: 106.5 cm2/(V s); subthreshold swing: 113.5 mV/decade; hysteresis: 0.05 V). In addition, the device shows minimal threshold voltage shifts of +0.45 and -0.10 V under harsh positive/negative bias temperature stress environments (field stress: ±2 MV/cm; temperature stress: 95 °C) after 10000 s.

Room temperature-grown highly oriented p-type nanocrystalline tellurium thin-films transistors for large-scale CMOS circuits

Although facile fabrication of high-performance thin-film transistor (TFT)-based complementary metal oxide–semiconductor (CMOS) circuits over a large area has generated significant interest, the lack of reliable and uniform p-type TFTs is hindering it. In this study, we prepared high-performance CMOS circuits using room temperature deposited nanocrystalline tellurium (nc-Te) and sputtered amorphous-indium gallium zinc oxide (a-IGZO) TFTs. The facile polyethyleneimine (PEI) surface treatment enabled Te atom anchoring and crystal orientation control along with continuous surface coverage, resulting in a high-performance TFT with an average mobility of 21.1 cm2V−1s−1 and an Ion/Ioff ratio of 104. By introducing monolithic integration of nc-Te and a-IGZO TFTs, various CMOS circuits including inverter, NAND, and NOR circuits were fabricated and operated quite logically. Moreover, seven-stage ring oscillators comprising 14 cross-wired TFTs validated the cascading of multiple stages and device uniformity of the complementary system, achieving an oscillation frequency up to 392.16 kHz at VDD of 20 V. nc-Te on a PEI-treated surface offers a general route to producing high-performance and stable p-type semiconductors while ensuring compatibility with standard CMOS processing and large-scale on-chip device applications.

Hf-doped ZnO transistor with high bias stability and high field-effect mobility by modulation of oxygen vacancies and interfaces

ZnO-based thin film transistors (TFTs) with high bias stability are challenging due to the intrinsic defects and overhigh interface trap density. In this work, we fabricated Hf-doped ZnO films with different cycle ratio of Zn/Hf via atomic layer deposition and subsequent annealing treatment. The results show that the cycle ratio of Zn/Hf is optimized to be 10:1, and the corresponding atomic ratio is 2.24%. The threshold voltage and subthreshold swing of the devices are improved as the annealing temperature increases, owning to the decrease of the oxygen vacancies and interface trap density. Furthermore, we developed Hf-doped ZnO TFT with high bias stability by introducing HfO2 intermediate layer between the active layer and SiO2 dielectric layer, and the shift of threshold voltage is as low as -0.273 V, showing high bias stability. Also, the device has the high field-effective mobility of 52.4 cm2/Vs, low subthreshold swing of 0.68 V/dec and high Ion/Ioff of 3.6 × 108. The results indicate a promising fabrication method for high-performance ZnO-based TFTs, which may be applied in logic circuits, radio frequency identification and so on.

High-performance p-channel CuIBr thin-film transistor synthesized from solution in the atmosphere

The p-type transparent semiconductor CuI has a high potential to be used in thin film transistors (TFTs) due to high hole mobility and solution processability. However, the lower copper vacancy formation energy and the subsequent high hole concentration in CuI lead to a low on/off current ratio (ION/IOFF) for CuI TFT devices. The density functional theory results suggest that the copper vacancy formation energy increases with the CuBr content in the Br-doped CuI film, resulting in lower hole concentration. Alloying CuI with CuBr is proposed to reduce the hole concentration in the CuIBr alloy. The CuIBr TFTs with Br content ranging from 0% to 10% were fabricated using the solution method. It is found that the hole mobility decreases from 8 to 1 cm2 V−1 s−1, while the ION/IOFF ratio increases from 102 to 104 with the increasing Br content. The CuIBr TFT with 7.5% Br content exhibits a high hole mobility larger than 5 cm2 V−1 s−1 and high ION/IOFF ratio of 104, which paves the way for inorganic-based CMOS circuits on flexible and transparent substrates.

Design and analysis of high-performance double-gate ZnO nano-structured thin-film ISFET for pH sensing applications

This paper reports a high-performance double-gate zinc-oxide thin-film ion-sensitive field-effect transistor (DG-ZnO-ISFET) for pH sensing applications. The sensing mechanism of DG-ZnO-ISFET and a simulation model for pH sensing analysis are demonstrated herein. Various aspects of the device are elucidated through the study of channel conductance, electron density, energy band, and surface-potential profiles. The DG-ZnO-ISFETs enhance minor surface potential variations by capacitive coupling across the dielectrics of the top and bottom gates. Further, it operates by altering the bottom-gate voltage (VBG), obviating the need for a reference electrode system. The device depicts enhanced voltage sensitivity of 205.57 mV/pH, which is substantially 3.48 × greater than the Nernst limit sensitivity. In addition, the DG-ZnO-ISFET renders a maximum current sensitivity of 10.82 mA/mm.pH at VBG=5V. Furthermore, it exhibits high linearity in both voltage and current sensitivity, with the coefficient of determination (R2) values of 0.984 and 0.964, respectively. With their increased sensitivity and linearity, DG-ZnO-ISFETs have the potential device for next-generation biosensors.

High-Performance Thin-Film Transistors with ZnO:H/ZnO Double Active Layers Fabricated at Room Temperature.

H doping can enhance the performance of ZnO thin-film transistors (TFTs) to a certain extent, and the design of double active layers is an effective way to further improve a device's performance. However, there are few studies on the combination of these two strategies. We fabricated TFTs with ZnO:H (4 nm)/ZnO (20 nm) double active layers by magnetron sputtering at room temperature, and studied the effect of the hydrogen flow ratio on the devices' performance. ZnO:H/ZnO-TFT has the best overall performance when H2/(Ar + H2) = 0.13% with a mobility of 12.10 cm2/Vs, an on/off current ratio of 2.32 × 107, a subthreshold swing of 0.67 V/Dec, and a threshold voltage of 1.68 V, which is significantly better than the performance of single active layer ZnO:H-TFTs. This exhibits that the transport mechanism of carriers in double active layer devices is more complicated. On one hand, increasing the hydrogen flow ratio can more effectively suppress the oxygen-related defect states, thus reducing the carrier scattering and increasing the carrier concentration. On the other hand, the energy band analysis shows that electrons accumulate at the interface of the ZnO layer close to the ZnO:H layer, providing an additional path for carrier transport. Our research exhibits that the combination of a simple hydrogen doping process and double active layer construction can achieve the fabrication of high-performance ZnO-based TFTs, and that the whole room temperature process also provides important reference value for the subsequent development of flexible devices.

Energy-band engineering by 2D MXene doping for high-performance homojunction transistors and logic circuits

The homojunction based on Ti3C2Tx MXene-doped In2O3 and indium oxide as the channel layer is realized in high-performance metal oxide thin film transistors (TFTs). Doping of MXene into In2O3 results in n-type semiconductor behavior, realizing tunable work function of In2O3 from 5.11 to 4.79 eV as MXene content increases from 0 to 2 wt.%. MXene-doped In2O3-based homojunction TFT presents optimal performance with electron mobilities of greater than 27.10 cm2/(V s) at 240 °C, far exceeding the maximum mobility of 3.91 cm2/(V s) for single-layer In2O3 TFTs. The improved performance originates from boosting of a two-dimensional electron gas (2DEG) formed at carefully engineered In2O3/MXene-doped In2O3 oxide homojunction interface. Besides, the transformation in conduction mechanism leads to better stability of MXene-doped In2O3 homojunction devices compared to undoped bilayer In2O3. Low-frequency noise further illustrates that doping MXene into In2O3 helps to reduce the device trap density, demonstrating excellent electrical performance. A resistor-loaded unipolar inverter based on In2O3/0.5% MXene-In2O3 TFT has demonstrated full swing characteristics and a high gain of 13. The effective doping of MXene into constructed homojunction TFTs not only contributes to improved stability, but also provides an effective strategy for designing novel homojunction TFTs for low-cost oxide-based electronics.

Self-Doping Naphthalene Diimide Conjugated Polymers for Flexible Unipolar n-Type OTFTs.

The development of high-performance organic thin-film transistor (OTFT) materials is vital for flexible electronics. Numerous OTFTs are so far reported but obtaining high-performance and reliable OTFTs simultaneously for flexible electronics is still challenging. Herein, it is reported that self-doping in conjugated polymer enables high unipolar n-type charge mobility in flexible OTFTs, as well as good operational/ambient stability and bending resistance. New naphthalene diimide (NDI)-conjugated polymers PNDI2T-NM17 and PNDI2T-NM50 with different contents of self-doping groups on their side chains are designed and synthesized. The effects of self-doping on the electronic properties of resulting flexible OTFTs are investigated. The results reveal that the flexible OTFTs based on self-doped PNDI2T-NM17 exhibit unipolar n-type charge-carrier properties and good operational/ambient stability thanks to the appropriate doping level and intermolecular interactions. The charge mobility and on/off ratio are fourfold and four orders of magnitude higher than those of undoped model polymer, respectively. Overall, the proposed self-doping strategy is useful for rationally designing OTFT materials with high semiconducting performance and reliability.

Selective Purity Modulation of Semiconducting Single-Walled Carbon Nanotube Networks for High-Performance Thin-Film Transistors

Single-walled carbon nanotube (SWCNT) random networks have become strong candidates for next-generation electronics due to their exceptional mechanical, electrical, and optical properties. However, metallic nanotubes in networks generally incur a trade-off between the charge carrier mobility and on/off ratio, limiting the performance of SWCNT-based devices. Therefore, various methods to increase the purity of semiconducting nanotubes in entire random networks have been reported, but this direction has faced other issues, such as nanotube shortening, higher cost, and higher energy. Here, we introduce SWCNT random network-based thin-film transistors (SWCNT TFTs) with a varying purity profile of semiconducting SWCNTs across the channel, exploiting the superior mobility of metallic SWCNTs by partially tuning the semiconducting SWCNT purity and developing a novel perspective on metallic nanotubes in semiconductor channels. Based on the high-precision drop-on-demand capability of inkjet printing and various concentrations of semiconducting SWCNT ink, we form selectively patterned channel regions with different semiconducting SWCNT purities. The metallic nanotube-dominant region drastically increases the carrier density with a minimized Schottky barrier, while high-purity semiconducting regions at the channel boundaries effectively block off-state leakage through carrier depletion. As a result, the SWCNT TFTs with selectively patterned metallic nanotube regions show superior carrier mobility (75.50 cm2 V–1 s–1) and channel width normalized on-current (34.33 nA μm–1) without compromising the on/off ratio (1.62 × 107). To show the feasibility of our device in high-performance electronics, we demonstrate all-inkjet-printed flexible display driving circuits with two transistors that enable low-power, high-performance operation in display applications.

Diketopyrrolopyrrole-based Conjugated Polymers as Representative Semiconductors for High-Performance Organic Thin-Film Transistors and Circuits

Diketopyrrolopyrrole-based Conjugated Polymers as Representative Semiconductors for High-Performance Organic Thin-Film Transistors and Circuits

High Field-Effect Mobility and On/Off Current Ratio of p-Type ALD SnO Thin-Film Transistor

High-performance p-type thin-film transistors (TFTs) with high field-effect mobility and high on/off current ratios (Ion/Ioff) were fabricated by engineering the microstructure and surface morphology of the atomic layer-deposited (ALD) SnO channel layer. ALD SnO films grown at a deposition temperature of 225 °C showed excellent crystallinity and dense, smooth surfaces, which resulted in superior field-effect mobility of 6.13–7.24 cm2/V·s without using a high-temperature postannealing process. Optimization of the SnO channel thickness suppressed the off-state leakage current, which consequently yielded excellent TFT switching performance, with an Ion/Ioff value of 104–105. Additionally, backchannel passivation by the ALD Al2O3 film improved the subthreshold swing characteristics by reducing surface defect states. These results suggest that synergistic control of the microstructure, surface morphology, and thickness of ALD SnO channels is crucial for achieving high-performance p-type SnO TFTs.

High-Performance Hexagonal Tellurium Thin-Film Transistor Using Tellurium Oxide as a Crystallization Retarder

This study investigates the effect of oxygen plasma (PO) on the crystalline structure of tellurium (Te) thin films during reactive sputtering. Introduction of oxygen radicals suppresses uncontrolled rapid growth of hexagonal Te crystals, amorphizing the deposited Te thin film. This amorphous phase changes to the hexagonal phase upon alumina encapsulation. A 4-nm-thick Te transistor with a PO of 7% exhibits outstanding device performances, with a field-effect mobility up to 40.8 cm2V−1s−1 and an on/off current modulation ratio up to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.1\times 10^{{6}}$ </tex-math></inline-formula> . These behaviors originate from alleviated random polycrystallinity in the corresponding thin film. However, when PO increases above 7%, amorphization progresses further, and remnant oxygen ions hamper the growth of the hexagonal phase in Te thin film. Consequently, hole transport is degraded. This study suggests tellurium oxide as a crystallization retarder for high-performance p-channel Te transistors.

Technique for Producing Metal Oxide Thin-Film Transistors at Low Temperatures

This research presents a novel method for manufacturing metal oxide thin-film transistors (TFTs) at low temperatures. The method involves coupling a metal-oxide film semiconductor to a thin film grid dielectric layer. By carefully controlling the combustion of a fuel-oxidant mixture, the desired metal-oxide film semiconductor is formed at temperatures below 350°C. This approach offers a cost-effective and scalable solution for producing high-performance TFTs on flexible plastic substrates.

High-Performance Amorphous InGaSnO Thin-Film Transistor with ZrAlOx Gate Insulator by Spray Pyrolysis

Here, we report the high-performance amorphous gallium indium tin oxide (a-IGTO) thin-film transistor (TFT) with zirconium aluminum oxide (ZAO) gate insulator by spray pyrolysis. The Ga ratio in the IGTO precursor solution varied up to 20%. The spray pyrolyzed a-IGTO with a high-k ZAO gate insulator (GI) exhibits the field-effect mobility (μFE) of 16 cm2V−1s−1, threshold voltage (VTH) of −0.45 V subthreshold swing (SS) of 133 mV/dec., and ON/OFF current ratio of ~108. The optimal a-IGTO TFT shows excellent stability under positive-bias-temperature stress (PBTS) with a small ΔVTH shift of 0.35 V. The enhancements are due to the high film quality and fewer interfacial traps at the a-IGTO/ZAO interface. Therefore, the spray pyrolyzed a-IGTO TFT can be a promising candidate for flexible TFT in the next-generation display.

Optimization of solution-processed amorphous cadmium gallium oxide for high-performance thin-film transistors

Cd-based materials, despite high electron mobility and wide bandgap, are understudied for thin-film transistors. Our study explores solution-processed cadmium gallium oxide as a high-performance thin-film transistors.

Self-Assembled Au/P3HT, High-k Bilayer Dielectric-Based Solution Processed Low Voltage OTFT for Multiparametric Ammonia Sensor at Room Temperature

A self-assembled, fully solution-processed, bilayer (TiO2/HfO2) dielectric-based thin film transistor (TFT) has been fabricated and explored for highly sensitive ammonia gas at room temperature (RT—25 °C). The bilayer dielectric film has been grown over a heavily boron-doped silicon substrate (p++ Si), and the thickness of each layer has been optimized by spin coating rotation speed and spin time to find a high-quality gate oxide. The obtained dielectric has a high areal capacitance of 0.926 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{F}$ </tex-math></inline-formula> /cm2, low rms roughness of 0.914 nm, and low leakage current density of ~1 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{A}$ </tex-math></inline-formula> /cm2, high dielectric constant of ~42, which are much more favorable for the high-performance organic TFT (OTFT). The incorporation of the TiO2 layer in between the p++ Si and HfO2 layer enhances the areal capacitance and minimizes the rms roughness (TiO2 minimizes the no. of interface trap states at the dielectric/semiconductor interface) of the bilayer dielectric film, thereby improving the charge transfer mechanism. The developed high- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${k}$ </tex-math></inline-formula> bilayer solution-processed dielectric layer has been utilized to develop a low voltage operated (−1.5 V) OTFT for ammonia (NH3) gas at RT. The fabricated OTFT device utilized the solution-processed floating film transfer method (FTM) to grow the Au(gold) doped P3HT film as a sensing/organic semiconductor channel (OSC) layer. The Au/P3HT sensing layer shows a quick response/recovery time (5/17 s), with a high sensing response of 55% (5 ppm) toward the NH3 analyte. The study aims to find a low-voltage, solution-processed, cost-efficient OTFT device for a high-performance gas sensor at RT.

Achieving High-Performance Solution-Processed Thin-Film Transistors by Doping Strong Reducibility Element Into Indium-Zinc-Oxide

Achieving High-Performance Solution-Processed Thin-Film Transistors by Doping Strong Reducibility Element Into Indium-Zinc-Oxide