High-performance Thin-film Transistors Research Articles

Improvement of Device Characteristics of Low Temperature IGZO Thin-film Transistors through Laser Post Annealing

High-performance thin-film transistors (TFTs) produced at low temperatures are required for ultrahigh- resolution and flexible display applications. The scientific community has been studying unconventional techniques to investigate low voltage flexible devices and low power flexible circuits for the past decade. In particular, metal oxide semiconductors, such as indium gallium zinc oxide (IGZO), have made significant progress as amorphous silicon replacements for electronics and commercial displays. On the other hand, developing metal oxide transistors with low processing temperatures remains a difficulty. The hightemperature annealing process causes very instability in the plastic substrate. Here, we introduce IGZO TFTs that shows enhanced electrical properties environmental stability by laser post-annealing. After annealing process, the laser post-annealing process was given at 80 MHz, pulse width 140 fs, for 50 seconds. The improved electrical characteristics of this laser post-annealed IGZO TFTs were: 9.03 cm<sup>2</sup>/Vs; 2.2×10<sup>7</sup> on/off current ratio. The IGZO TFT to which laser post-annealing was applied had a flat surface, and it was confirmed that the combination of internal metal and oxygen was urged, and the leakage current problem was improved by suppressing excessive generation of oxygen vacancy. Furthermore, the voltage transfer curve was measured after fabricating the N-MOS logic inverter circuit, this inverter showed a value of 80.8% the total noise margin.

High-performance polymer top-contact thin-film transistor with orthogonal photolithographic process

Based on fluorinated photoresist, an orthogonal lift-off process was introduced to directly fabricate patterning metallic source and drain contacts on polymeric thin films to obtain the top-contact structure device. Top-contact polymeric thin-film transistors (TFTs) on the wafer using this orthogonal lift-off process exhibited excellent value of electrical characteristics which was as high as 2.56 cm2V−1s−1 in mobility and >107 in on/off ratio. Compared with Ref. device which was fabricated by shadow mask, this top-contact polymeric TFTs showed the same mobilities but smaller channel length, and the lower contact resistance. In addition, based on fluorinated photoresist, the top-contact polymeric TFTs backplane with photo-patternable expoxy gate insulating layer was also successfully fabricated on glass. The mobility values of this OTFTs with different channel lengths ranged from 0.25 to 0.74 cm2V−1s−1 with an average of 0.48 ± 0.15 cm2V−1s−1 which can be comparable to the Ref. device with epoxy gate insulator using shadow mask method. It was further proved that the availability of such orthogonal photoresists promised to enable the fabrication of high performance OTFT device based the copolymer with long linear alkyl chains.

Sol-gel-based metal-oxide thin-film transistors for high-performance flexible NMOS inverters

High-performance metal-oxide thin-film transistors (oxide-TFTs) with high-k zirconium dioxide (ZrO2) dielectric and indium-gallium-zinc oxide (IGZO) semiconducting films were developed on flexible polyimide substrates. The flexible IGZO-TFTs fabricated using a simple and effective sol-gel-based solution-process combined with oxygen-enriched consecutive annealing at 200 °C, exhibited a high field-effect mobility of 13.6 cm2 V−1 s−1 at 5 V, on/off ratio of 1.05 × 106, gate leakage current of 2.7 × 10−11 A, and threshold voltage of 0.44 V. The effects of O2 annealing on the film quality of the sol-gel-based ZrO2 and IGZO were investigated by analyzing the crystallinity, morphology, and degree of metal-oxygen bonding states. Temperature-dependent steady-state direct-current measurements over the temperature range of 90–300 K, and time-domain non-quasi-static transient measurements with a minimized resistance-capacitance time constant were performed. Thus, the activation energy, density of states, interface trap density, and velocity distribution were determined to investigate the charge transport mechanism responsible for the high performance of the oxide- TFTs proposed in this study. An enhancement-load-type N-channel metal-oxide semiconductor (NMOS) inverter consisting of two oxide-TFTs fabricated via O2 annealing was demonstrated. The flexible NMOS inverter exhibited a high gain of 10.8 at 5 V and outstanding mechanical stability against 10,000 cycles of bending stresses at a strain of 30% without a passivation or buffer film.

Performance improvement of thin-film transistors with In2O3 channel engineering

ABSTRACT Thin-film transistors (TFTs) with bilayer channels were used to improve the field-effect mobility and bias stress stability of the TFTs. Homogeneous structures were fabricated by the combination of a carrier deficient layer made of In2O3 thin film annealed in oxygen atmosphere (InO:O) and an electron injection layer made of In2O3 thin film annealed in air (InO:A). Compared with the InO:A/InO:A TFT with only air annealing, the field-effect mobility of InO:O/ InO:A TFT with two-step annealing process was improved from 0.04 to 5.11 cm2/Vs, the on/off current ratio was ameliorated from 4.6 × 105 to 7.6 × 107 A, while the VTH is decreased from 12.5 to 4.7 V under the positive bias stressing (PBS). It is confirmed that the excessive oxygen vacancies are produced by annealing the thin film in the air. The electrical performance of the InO:O/InO:A TFTs with two-step annealing process is greatly improved due to the formation of a low defect state and high carrier concentration electron transport layer, through the combination of the carrier transport layer and the carrier injection layer. These optimized electrical properties indicate an important step toward achieving transparent, high performance, and low-temperature metal oxides TFTs.

IZO Thin Film Transistor-Oriented Trap State UV Analysis Using Random Matrix

With the popularization of electronic equipment, indium zinc oxide (IZO) thin film transistor (TFT) research has become a hot spot. Due to the excellent characteristics of solution method, solution-processed IZO TFTs have seen wide applications in various fields. However, the study on the trapping state distribution of solution-processed IZO TFTs is not thorough enough, and the current research methods have limitations. Therefore, the ultraviolet (UV) analysis method is introduced for analyzing the trap state distributions. Then, the UV analysis method is optimized using the random matrix. The interface and bulk trap states are extracted, and the feature of trap states is analyzed. Experimental results show that under the proposed method, the bulk trap concentration of IZO TFTs is 1018∼1019 cm−3 eV−1, and the interface state density is 1012∼1013 cm−2V−1. They all change with wavelength. The proposed method is effective, feasible, and easy to implement. The research will make an important contribution to the preparation of high-performance IZO TFTs.

High-performance n-type thin-film transistor based on bilayer MXene/semiconductor with enhanced electrons transport

Interfacial engineering at the dielectric/semiconductor interface is highly crucial for fabricating organic field-effect transistors with high performance. In this study, a bilayer MXene/semiconductor configuration is introduced to fabricate a high-performance n-type transistor, where electrical charges are formed and modulated at the SiO2/semiconductor interface, and MXene nanosheets serve as the primary electrical charge channel due to their high mobility and long lateral size. The electrical performance is optimized by adjusting the degree of connectivity of the MXene nanosheets. The proposed MXene/poly{[N,N′-bis(2-octyl-do-decyl)-naphthalene-1,4,5,8-bis(dicarboximide)-2,6-diyl]-alt-5,5′-(2,2′-bithiophene)} (N2200) transistors show boosted n-type characteristics, including a 100-fold increase in field-effect mobility, a large ON/OFF ratio of 104, and a small subthreshold swing of 0.65 V dec−1, all of which are significantly improved compared with single-layer N2200 transistors. The high performance of the two-dimensional MXene nanochannel is due to its electronegativity and high mobility. The electronegativity significantly enhances electron transfer from N2200 to the MXene channel, where they are efficiently transported along the MXene channel. Interestingly, the MXene/p-type semiconductor transistors show suppressed p-type performance because of the highly negative MXene nanosheets. Additionally, the proposed bilayer MXene/n-type semiconductor configuration shows a good configuration generality and improved performance. These findings demonstrate the feasibility of fabricating high-performance n-type transistors using a bilayer MXene/semiconductor combination.

Impact of electrode materials on the performance of amorphous IGZO thin-film transistors

This study reports on the fabrication and characterization of thin-film transistors (TFTs) based on indium–gallium–zinc–oxide (IGZO) with various source- and drain-region metals (Pt, W and Ti). The performance of the IGZO transistors is compared to TFTs based on hydrogenated amorphous silicon (a-Si:H) with Pt source- and drain-regions. From the output characteristics maximum saturation mobilities of µ = 0.45 cm2/Vs for a-Si:H, and µ = 24 to 50 cm2/Vs for IGZO TFTs are extracted, which are competitive to high-performance thin-film transistors. The study reveals a general influence of the source- and drain-electrode material on the maximum saturation mobility and inverse sub-threshold slope.Graphical abstract

Gate Dielectric Treated by Self-Assembled Monolayers (SAMs) to Enhance the Performance of InSnZnO Thin-Film Transistors

Self-assembled monolayer (SAM) treatment of gate dielectrics is a standard process for manufacturing organic thin-film transistors (TFTs) to reduce interface trap density and surface energy. However, it is rarely used for oxide semiconductor-based TFTs because the SAMs may be damaged during the manufacturing process. To explore the feasibility of using a SAM-treated gate dielectric to improve the performance of oxide TFTs, we study the effects of different SAM treatments of the gate dielectric layer on the performance of InSnZnO (ITZO) TFTs, which can help guide the selection of SAMs. After treatment with methyltriethoxysilane (C1-SAM), the performance of the TFTs is significantly improved, showing a drastic improvement in the ON/ OFF ratio and carrier mobility, and a reduction of the interface trap density and <inline-formula> <tex-math notation="LaTeX">${V}_{\text {th}}$ </tex-math></inline-formula> shift of the device under positive/negative bias stress (PBS/NBS). However, after treatment with n-octyltriethoxysilane (C8-SAM) and octadecyltriethoxysilane (C18-SAM), the performance of the TFTs deteriorate or even fail. Nevertheless, this work demonstrates an effective strategy for the construction of high-performance metal oxide TFTs, though it may require careful selection of the SAMs.

Photonic Cured Metal Oxides for Low-Cost, High-Performance, Low-Voltage, Flexible, and Transparent Thin-Film Transistors

Photonic Cured Metal Oxides for Low-Cost, High-Performance, Low-Voltage, Flexible, and Transparent Thin-Film Transistors

Flexible Hybrid Single-Crystalline Silicon Nanomembrane Thin-Film Transistor with Organic Polymeric Polystyrene as a Gate Dielectric on a Plastic Substrate

Flexible thin-film transistors (TFTs) play an important role in flexible integrated circuits (ICs). Hybrid integrated transistors are highly desirable because of their high performance and simplified process. However, TFTs with a hybrid integrated heterostructure of single-crystalline semiconductor/organic dielectric layers have not yet been discussed. In this work, a flexible hybrid TFT comprised of a single-crystalline silicon nanomembrane (SiNM) semiconductor and polystyrene (PS) gate dielectric was fabricated on a PET substrate. The surface morphology of the PS dielectric layer on the PET substrate was characterized by scanning electron microscopy (SEM) and atomic force microscopy (AFM). The electrical characteristics of the dielectric layer (PS) were also analyzed. SiNM was processed with a complementary metal–oxide–semiconductor (CMOS)-compatible process and subsequently transferred to the PET substrate with a PS/ITO stacked layer to complete the assembly of the flexible hybrid SiNM/PS TFT. The electrical properties of the flexible hybrid TFT were characterized under different bending conditions (i.e., flat and bending radii of 21, 38.5, and 77.5 mm). Furthermore, the stress analysis of TFTs influenced by a variation of the dielectric materials (i.e., PS, SiO2, and Al2O3), the adhesion conditions of the SiNM/PS interface, and the dielectric thickness were also discussed. The results revealed the potential of combining an organic polymeric dielectric with inorganic single-crystalline nanomembranes to fabricate high-performance flexible hybrid TFTs.

Comparative Study of Atomic Layer Deposited Indium-Based Oxide Transistors with a Fermi Energy Level-Engineered Heterojunction Structure Channel through a Cation Combinatorial Approach.

Amorphous indium-gallium-zinc oxide (a-IGZO) has become a standard channel ingredient of switching/driving transistors in active-matrix organic light-emitting diode (AMOLED) televisions. However, mobile AMOLED displays with a high pixel density (≥500 pixels per inch) and good form factor do not often employ a-IGZO transistors due to their modest mobility (10-20 cm2/(V s)). Hybrid low-temperature polycrystalline silicon and oxide transistor (LTPO) technology is being adapted in high-end mobile AMOLED devices due to its ultralow power consumption and excellent current drivability. The critical issues of LTPO (including a complicated structure and high fabrication costs) require a search for alternative all-oxide thin-film transistors (TFTs) with low-cost processability and simple device architecture. The atomic layer deposition (ALD) method is a promising route for high-performance all-oxide TFTs due to its unique features, such as in situ cation composition tailoring ability, precise nanoscale thickness controllability, and excellent step coverage. Here, we report an in-depth comparative investigation of TFTs with indium-gallium oxide (IGO)/gallium-zinc oxide (GZO) and indium-zinc oxide (IZO)/GZO heterojunction stacks using an ALD method. IGO and IZO layers with different compositions were tested as a confinement layer (CL), whereas the GZO layer was used as a barrier layer (BL). Optimal IGO/GZO and IZO/GZO channels were carefully designed on the basis of their energy band properties, where the formation of a quasi-two-dimensional electron gas (q2DEG) near the CL/BL interface is realized by rational design of the band gaps and work-functions of the IGO, IZO, and GZO thin films. To verify the effect of q2DEG formation, the device performances and stabilities of TFTs with CL/BL oxide heterojunction stacks were examined and compared to those of TFTs with a single CL layer. The optimized device with the In0.75Zn0.25O/Ga0.80Zn0.20O stack showed remarkable electrical performance: μFE of 76.7 ± 0.51 cm2/(V s), VTH of -0.37 ± 0.19 V, SS of 0.13 ± 0.01 V/dec, and ION/OFF of 2.5 × 1010 with low operation voltage range of ≥2 V and excellent stabilities (ΔVTH of +0.35, -0.67, and +0.08 V for PBTS, NBIS, and CCS, respectively). This study suggests the feasibility of using high-performance ALD-derived oxide TFTs (which can compete with the performance of LTPO transistors) for high-end mobile AMOLED displays.

Combustion-assisted low-temperature solution process for high-performance SnO2 thin-film transistors

In this study, high-performance SnO2 thin-film transistors (TFTs) were fabricated at temperatures below 300 °C using the combustion-assisted sol-gel method. The internal energy induced by the exothermic reaction of the fuel and the oxidizer in the combustion precursors facilitates precursor conversion even at low processing temperatures, leading to the development of crystalline SnO2. Compared to the conventional solution process, it was confirmed that the precursor was converted to crystalline SnO2 at below 300 °C through thermogravimetric analysis, differential scanning calorimetry, and grazing incidence X-ray diffraction. In addition, X-ray photoelectron spectroscopy spectra indicate the formation of complete metal-oxygen-metal networks with an increase in the oxygen corresponding to the lattice, as well as a decrease in hydroxyl groups. As a result, compared with the conventional SnO2 TFTs, the field-effect mobility of combustion-assisted SnO2 TFTs increased significantly from 0.014 ± 0.01 to 2.43 ± 0.22 cm2/Vs at 250 °C (by ∼ 170 times) and from 0.38 ± 0.15 to 6.53 ± 0.41 cm2/Vs at 300 °C (by ∼ 17 times). Therefore, the combustion-assisted solution process is expected not only to realize fully low-cost solution-processed electronics by fabricating high-quality SnO2 at low temperatures, but also to be combined with plastic substrates to fabricate flexible electronics.

Insulating Polymer Blend Organic Thin-Film Transistors Based on Bilayer-Type Alkylated Benzothieno[3,2-b]naphtho[2,3-b]thiophene.

Herein, we developed a practical method to produce high-performance organic thin-film transistors (OTFTs) based on highly layered crystalline organic semiconductors (OSCs) that form bilayer-type layered herringbone (b-LHB) packing and exhibit high intrinsic mobility. We applied the insulating polymer blend technique using a typical b-LHB OSC of 2-octyl-benzothieno[3,2-b]naphtho[2,3-b]thiophene (2-C8-BTNT) and fabricated polycrystalline thin-film transistors (TFTs) via short-duration spin coating and subsequent annealing. The use of blends and the choice of polymer additive strongly affected the performance of the polycrystalline TFTs, and poly(methyl methacrylate) (PMMA) blend TFTs exhibited a high mobility exceeding 4 cm2/(V s) and small device-to-device variations. Using extended techniques in atomic force microscopy (AFM), we investigated the thin-film morphologies by bimodal AFM and the carrier transport properties by Kelvin probe force microscopy (KPFM). We demonstrated that the PMMA blend system enables the formation of a well-ordered polycrystalline thin film induced by vertical phase separation between the OSC and PMMA over a large area, resulting in uniform TFT performance. These findings pave the way for obtaining high-performance TFTs using simple processes, representing a substantial advancement toward the realization of printed electronics.

High-performance hysteresis-free perovskite transistors through anion engineering

Despite the impressive development of metal halide perovskites in diverse optoelectronics, progress on high-performance transistors employing state-of-the-art perovskite channels has been limited due to ion migration and large organic spacer isolation. Herein, we report high-performance hysteresis-free p-channel perovskite thin-film transistors (TFTs) based on methylammonium tin iodide (MASnI3) and rationalise the effects of halide (I/Br/Cl) anion engineering on film quality improvement and tin/iodine vacancy suppression, realising high hole mobilities of 20 cm2 V−1 s−1, current on/off ratios exceeding 107, and threshold voltages of 0 V along with high operational stabilities and reproducibilities. We reveal ion migration has a negligible contribution to the hysteresis of Sn-based perovskite TFTs; instead, minority carrier trapping is the primary cause. Finally, we integrate the perovskite TFTs with commercialised n-channel indium gallium zinc oxide TFTs on a single chip to construct high-gain complementary inverters, facilitating the development of halide perovskite semiconductors for printable electronics and circuits.

Water-Processed Ultrathin Crystalline Indium-Boron-Oxide Channel for High-Performance Thin-Film Transistor Applications.

Thin-film transistors (TFTs) made of solution-processable transparent metal oxide semiconductors show great potential for use in emerging large-scale optoelectronics. However, current solution-processed metal oxide TFTs still suffer from relatively poor device performance, hindering their further advancement. In this work, we create a novel ultrathin crystalline indium–boron–oxide (In-B-O) channel layer for high-performance TFTs. We show that high-quality ultrathin (~10 nm) crystalline In-B-O with an atomically smooth nature (RMS: ~0.15 nm) could be grown from an aqueous solution via facile one-step spin-coating. The impacts of B doping on the physical, chemical and electrical properties of the In2O3 film are systematically investigated. The results show that B has large metal–oxide bond dissociation energy and high Lewis acid strength, which can suppress oxygen vacancy-/hydroxyl-related defects and alleviate dopant-induced carrier scattering, resulting in electrical performance improvement. The optimized In-B-O (10% B) TFTs based on SiO2/Si substrate demonstrate a mobility of ~8 cm2/(V s), an on/off current ratio of ~106 and a subthreshold swing of 0.86 V/dec. Furthermore, by introducing the water-processed high-K ZrO2 dielectric, the fully aqueous solution-grown In-B-O/ZrO2 TFTs exhibit excellent device performance, with a mobility of ~11 cm2/(V s), an on/off current of ~105, a subthreshold swing of 0.19 V/dec, a low operating voltage of 5 V and superior bias stress stability. Our research opens up new avenues for low-cost, large-area green oxide electronic devices with superior performance.

Modulation of vacancy-ordered double perovskite Cs2SnI6 for air-stable thin-film transistors

Vacancy-ordered halide double perovskites are promising non-toxic and stable alternatives for their lead- and tin (II)-based counterparts in electronic and optoelectronic applications. Despite extensive theoretical studies on this emerging family of materials, efforts devoted to the chemical modulation of their thin-film properties and their potential application in electronic devices remain rare. Here, we develop a facile one-step solution processing strategy to tune the film quality of cesium tin (IV) iodide (Cs 2 SnI 6 ) perovskite and demonstrate its feasibility in thin-film transistor (TFT) application. We reveal critical roles of precursor stoichiometric ratio and solvent engineering in achieving uniform and highly crystalline Cs 2 SnI 6 films with superior electron mobility. We further modulate the electronic properties by incorporating an external manganese (Mn 2+ ) dopant, achieving high-performance air-stable n-channel TFTs and all-perovskite complementary inverters. We anticipate that the present study would pave the way for expanding the environmentally friendly and stable perovskites toward widespread applications. • Precursor engineering for one-step solution deposition of Cs 2 SnI 6 thin films • Electrical modulation of the Cs 2 SnI 6 perovskite for transistor application • Integrated transistors exhibit appealing electrical performance with high stability Liu et al. report the deposition of eco-friendly vacancy-ordered double perovskite Cs 2 SnI 6 thin films using a one-step solution process. Subsequently, an external atomic doping is adopted to modulate the electrical property of the Cs 2 SnI 6 perovskite. The resulting transistors exhibit appealing electrical performance with highly stable characteristics.

Ultraviolet-Assisted Low-Thermal-Budget-Driven α-InGaZnO Thin Films for High-Performance Transistors and Logic Circuits.

Developing a low-temperature fabrication strategy of an amorphous InGaZnO (α-IGZO) channel layer is a prerequisite for high-performance oxide-based thin film transistor (TFT) flexible device applications. Herein, an ultraviolet-assisted oxygen ambient rapid thermal annealing method (UV-ORTA), which combines ultraviolet irradiation with rapid annealing treatment in an oxygen atmosphere, was proposed to realize the achievement of high-performance α-IGZO TFTs at low temperature. Experimental results have confirmed that UV-ORTA treatment has the ability to suppress defects and obtain high-quality films similar to high-temperature-annealing-treated samples. α-IGZO/HfAlO TFTs with high-performance and low-voltage operating have been achieved at a low temperature of 180 °C for 200 s, including a high μsat of 23.12 cm2 V-1 S-1, large Ion/off of 1.1 × 108, small subthreshold swing of 0.08 V/decade, and reliable stability under bias stress, respectively. As a demonstration of complex logic applications, a low-voltage resistor-loaded unipolar inverter based on an α-IGZO/HfAlO TFT has been built, demonstrating full swing characteristics and a high gain of 13.8. Low-frequency noise (LFN) characteristics of α-IGZO/HfAlO TFTs have been presented and concluded that the noise source tended to a carrier number fluctuation (ΔN) model from a carrier number and correlated mobility fluctuation (ΔN-Δμ) model. As a result, it can be inferred that the low-temperature UV-ORTA technique to improve α-IGZO thin film quality provides a facile and designable process for the integration of α-IGZO TFTs into a flexible electronic system.

Effects of Blended Poly(3-hexylthiophene) and 6,13-bis(triisopropylsilylethynyl) pentacene Organic Semiconductors on the Photoresponse Characteristics of Thin-Film Transistors

In this study, we demonstrate high-performance optical wavelength-selective organic thin-film transistors (TFTs) that incorporate heterogeneous organic semiconductor materials, poly(3-hexylthiophene) (P3HT) and 6,13-bis(triisopropylsilylethynyl) pentacene (TIPS-pentacene). The electrical characteristics of the fabricated transistors were analyzed in the dark to determine how the P3HT:TIPS-pentacene ratio of the semiconductor affected the performance of the transistor. Specifically, the P3HT:TIPS-pentacene weight ratio was varied (1:0, 1:0.25, 1:0.5, 1:0.75, 1:1, and 0:1) by blending 1 wt% P3HT dissolved in chloroform, and 1 wt% TIPS-pentacene dissolved in anisole. The UV-visible light absorbance characteristics of the films containing the P3HT, TIPS-pentacene, and P3HT:TIPS-pentacene blends were analyzed. Monochromatic light at wavelengths of 515 and 450 nm was used to clarify the influence of irradiation on the electrical characteristics of the TFTs. The results confirmed that the TFT containing P3HT:TIPS-pentacene at a blending ratio of 1:0.5 had the largest light-to-dark current ratio, i.e., approximately 33.8 and 23.5 when exposed to monochromatic light at wavelengths of 515 nm and 450 nm, respectively. The TFT with the P3HT:TIPS-pentacene blending ratio of 1:0.5 exhibited the highest photosensitivity values of 261.9 and 49.6 upon irradiation with light at wavelengths of 515 nm and 450 nm, respectively. The observed improvement in the performance of the heterogeneously blended organic transistors is discussed in relation to the morphological structure and charge transport path of the P3HT:TIPS-pentacene blended semiconductor films.

Organic-Inorganic Hybrid Gate Dielectrics Using Self-Assembled Multilayers For Low-Voltage Operating Thin-Film Transistors

Advanced electronic materials have attracted great interest for their potential use in flexible, large-area, and printable electronic applications. However, fabricating high-performance low-voltage thin-film transistors (TFTs) for those applications with these advanced semiconductors is still challenging because of a lack of dielectric materials which satisfy both the required electrical and physical performance. In this work, we report self-assembled hybrid multilayer gate dielectrics prepared using a facile solution procedure to achieve organic semiconductor and amorphous oxide semiconductor-based thin-film transistors with ultralow operating voltage. These self-assembled hybrid multilayer gate dielectrics were constructed by iterative self-assembly of synthesized bifunctional phosphonic acid-based organic molecules and ultrathin high-k hafnium oxide layers. The novel self-assembled hybrid multilayer gate dielectrics exhibit excellent dielectric properties with exceptionally large capacitances (up to 815 nF/ cm2) and low-level leakage current densities of &lt; 1.56 × 10-6 A/cm2, featureless morphology (RMS roughness &lt; 0.24 nm), and thermal stability (up to 300 °C). Consequently, these hybrid gate dielectrics can be incorporated into thin-film transistors with pentacene as p-type organic semiconductors, and with indium oxide as n-type inorganic semiconductors. The resulting TFTs functioned at ultralow voltages (&lt; ± 2 V) and achieved high transistor performances (hole mobility: 0.88 cm2 / V·s, electron mobility: 7.8 cm2 / V·s and on/off current ratio &gt;104, and threshold voltage: ± 0.5 V).

High-Performance Thin-Film Transistors and Inverters Based on ALD-Derived Ultrathin Al2O3-Passivated CeO2 Bilayer Gate Dielectrics

In this article, solution-derived amorphous cerium oxide (CeO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ) with smooth surface as gate dielectric has been investigated. Electrical analysis has indicated that ALD-derived 3 nm Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> passivation layer on CeO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> surface is benefit to reduce leakage current of CeO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> MOS capacitors. Meanwhile, solution-processed In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> thin-film transistors (TFTs) based on optimized Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> /CeO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> bilayer dielectric are integrated for the first time. Results indicate that 300 °C annealed In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> /Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> /CeO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> TFT presents high performances with saturation mobility of 18.25 ± 0.92 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> / <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{V}\cdot \text{s}$ </tex-math></inline-formula> , <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ </tex-math></inline-formula> ratio of (1.81 ± 0.30) <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times \,\,10^{{7}}$ </tex-math></inline-formula> , subthreshold swing of 0.071 ± 0.002 V/decade, interfacial trap states ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${D}_{\,\text {it}}$ </tex-math></inline-formula> ) of (6.00 ± 0.48) <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times \,\,10^{{11}}$ </tex-math></inline-formula> cm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{-{2}}$ </tex-math></inline-formula> , and remarkable positive bias stress (PBS) stability, respectively. Furthermore, a resistor-loaded inverter is fabricated with voltage gain of 12.81 at 5 V and good voltage-transfer characteristics (VTCs), demonstrating the potential application of Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> /CeO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> as high- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${k}$ </tex-math></inline-formula> gate stacks for future TFTs.