High-level Synthesis Methodology Research Articles

Exploration of optimal functional Trojan-resistant hardware intellectual property (IP) core designs during high level synthesis

Hardware Trojans that have the capability to change the computed functional output in intellectual property (IP) cores, integrated into computing systems can be a vital reliability concern in the context of correct system operation. Therefore, determining an optimal Trojan-resistant hardware design architecture that considers multi-objective orthogonal parameters such as area and delay is crucial. This paper presents a novel exploration of optimal hardware IP core design methodology with Trojan defense capability (i.e., detection and isolation) during high level synthesis (HLS) that provides isolation of functional Trojan in a system design to ensure reliable and correct functional behavior. The proposed methodology is robust and provides the capability to yield the correct output value using HLS-based triple modular redundancy (TMR) logic and a distinct multivendor allocation policy. Therefore, the proposed HLS methodology can generate an optimal hardware IP core/system-on-chip (SoC) design with functional Trojan defense capability. The paper presents an overall flow of the proposed methodology along with a demonstrative case study on designing optimal Trojan resistant finite impulse response filter (FIR) hardware SoC design. Results of the proposed approach are evaluated in terms of design cost, convergence time, security and optimality analysis, and comparison with prior works. The proposed approach is able to generate fully functional Trojan-resistant optimal SoC designs with minimum overhead, as evident from optimality analysis and design cost.

Real-time energy-efficient software and hardware implementations of a QCSP communication system

In the Internet of Things, the energy efficiency of communications is crucial. Thus, using data-less preambles to detect frames is suboptimal. A preamble-less physical layer named “Quasi-Cyclic Short Packet (QCSP)” proposed a solution. However, the high computational complexity of the receiver makes the implementation challenging. This paper studies the feasibility and efficiency of real-time software and hardware QCSP systems. Several highly efficient transmitter implementations are presented, demonstrating the relevance of the approach. The parallelization and optimization strategies are elaborated for both software and hardware receiver implementations. They allowed software implementations with throughputs above 50 kb/s (maximum for the LoRa standard), consuming as low as 27 μJ/b. Thanks to detailed algorithm refinements, the throughtput even exceeded 250 kb/s on FPGA using High-Level Synthesis methodology, for an estimated consumption of 3.9 μJ/b. The results support the viability of the QCSP approach for cloud-RAN and edge computing in Low-Power Wide-Area Networks.

Integer linear programming-based optimization methodology for reliability and energy-aware high-level synthesis

Continuous decrease in the transistor technology sizes has enabled much denser packaging of electronic components on chips, which has resulted in integrated circuits with lower costs and area. However, it has also given rise to new issues and challenges in the process of integrated circuit design, including higher vulnerability to soft errors. Modular hardware redundancy is a popular method for improving the reliability of a system against errors at a cost of increasing area and energy consumption. Voltage scaling methods can be employed to tackle high energy costs; however, this also negatively affects the circuit’s reliability and performance. Therefore, designing circuits with all these conflicting parameters is a very challenging task. In this study, we propose integer linear programming (ILP)-based high-level synthesis (HLS) methods to optimize both reliability and/or energy under the area and latency constraints. Our models employ full and partial duplication to improve the system reliability as long as the area constraint permits. They also utilize voltage islands as the energy reduction method of choice. What makes this problem even more interesting and complex is the fact that we use different versions of the same resources that have different area, latency, reliability, and energy values. Although this affects the execution time of the proposed methods, it also gives us more design options. We compared and showed the effectiveness of our methods against a genetic algorithm-based one on several HLS benchmarks. The ILP-based methods return the optimum results most of the time under the given time limits.

A High-Level Synthesis Methodology for Energy and Reliability-Oriented Designs

Shrinking technology sizes of the CMOS circuits makes it possible to place more transistors on a single chip at each technology generation. On the other hand, circuits become more vulnerable to radiation effects due to lower supply and threshold voltage levels; thus, the number of transient faults in circuits tends to increase. Moreover, energy reduction techniques also negatively affect the reliability of circuits. Traditional high-level synthesis (HLS) methods usually consider only area and latency along with either energy or reliability. Especially the effect of using different voltage levels on reliability is completely ignored by previous studies. In this article, we present two new HLS methods for application-specific integrated circuit (ASIC) design under area and timing constraints with the objectives of low energy consumption and high reliability. For the mapping and scheduling steps of HLS, we propose integer linear programming (ILP) and genetic algorithm (GA)-based optimization methods. While ILP provides the optimum results, the CPU time increases exponentially with the number of application nodes. On the other hand, GA-based metaheuristic is faster and determines optimum or near-optimum results in shorter times than ILP. Additionally, we use a selective duplication method to further improve the overall reliability.

FPGA-based implementation of a chirp signal generator using an OpenCL design

A novel approach to developing an FPGA-based chirp signal generator using high-level synthesis implementation is proposed. OpenCL, which is a framework used for high-level synthesis (HLS) methodologies, is employed instead of the Verilog/VHDL language to program FPGA. OpenCL has been used for FPGA programming, particularly in high-performance computing applications. Utilizing OpenCL for FPGA development reduces development time because of the high-level abstraction of the code. However, compared to Verilog/VHDL, standard OpenCL does not enable direct access to the FPGA's I/O. In this study, the FPGA needs to access the I/O pins to communicate with the DAC and generate the chirp signal. Thus, direct access to the FPGA I/O pin from the OpenCL environment is required. Therefore, a new OpenCL component is developed to enable the FPGA to communicate with the DAC, thus allowing data streaming to generate the chirp signal. This OpenCL component enables us to stream the data from the FPGA to generate the chirp signal. Here, we demonstrate that by using OpenCL implementation, the FPGA can generate an I/Q chirp signal efficiently. Moreover, the same OpenCL kernel can be employed to generate different bandwidths of the chirp signal without having to reprogram the FPGA. To demonstrate the capability of the system, we generated the I/Q chirp signal from 1 MHz to 5 MHz, 5 MHz to 10 MHz, 10 MHz to 15 MHz and 15 MHz to 20 MHz for a period of 10 µs.

A Survey on Performance Optimization of High-Level Synthesis Tools

Field-programmable gate arrays (FPGAs) have recently evolved as a valuable component of the heterogeneous computing. The register transfer level (RTL) design flows demand the designers to be experienced in hardware, resulting in a possible failure of time-to-market. High-level synthesis (HLS) permits designers to work at a higher level of abstraction through synthesizing high-level language programs to RTL descriptions. This provides a promising approach to solve these problems. However, the performance of HLS tools still has limitations. For example, designers remain exposed to various aspects of hardware design, development cycles are still time consuming, and the quality of results (QoR) of HLS tools is far behind that of RTL flows. In this paper, we survey the literature published since 2014 focusing on the performance optimization of HLS tools. Compared with previous work, we extend the scope of the performance of HLS tools, and present a set of three-level evaluation criteria, covering from ease of use of the HLS tools to promotion on specific metrics of QoR. We also propose performance evaluation equations for describing the relation between the performance optimization and the QoR. We find that it needs more efforts on the ease of use for efficient HLS tools. We suggest that it is better to draw an analogy between the HLS development process and the embedded system design process, and to provide more elastic HLS methodology which integrates FPGAs virtual machines.

High-Level Synthesis of Multiclass SVM Using Code Refactoring to Classify Brain Cancer from Hyperspectral Images

Currently, high-level synthesis (HLS) methods and tools are a highly relevant area in the strategy of several leading companies in the field of system-on-chips (SoCs) and field programmable gate arrays (FPGAs). HLS facilitates the work of system developers, who benefit from integrated and automated design workflows, considerably reducing the design time. Although many advances have been made in this research field, there are still some uncertainties about the quality and performance of the designs generated with the use of HLS methodologies. In this paper, we propose an optimization of the HLS methodology by code refactoring using Xilinx SDSoCTM (Software-Defined System-On-Chip). Several options were analyzed for each alternative through code refactoring of a multiclass support vector machine (SVM) classifier written in C, using two different Zynq®-7000 SoC devices from Xilinx, the ZC7020 (ZedBoard) and the ZC7045 (ZC706). The classifier was evaluated using a brain cancer database of hyperspectral images. The proposed methodology not only reduces the required resources using less than 20% of the FPGA, but also reduces the power consumption −23% compared to the full implementation. The speedup obtained of 2.86× (ZC7045) is the highest found in the literature for SVM hardware implementations.

TaintHLS: High-Level Synthesis for Dynamic Information Flow Tracking

Dynamic information flow tracking (DIFT) is a technique to track potential security vulnerabilities in software and hardware systems at run time. Untrusted data are marked with tags (tainted), which are propagated through the system and their potential for unsafe use is analyzed to prevent them. DIFT is not supported in heterogeneous systems especially hardware accelerators. Currently, DIFT is manually generated and integrated into the accelerators. This process is error-prone, potentially hurting the process of identifying security violations in heterogeneous systems. We present TaintHLS, to automatically generate a micro-architecture to support baseline operations and a shadow microarchitecture for intrinsic DIFT support in hardware accelerators while providing variable granularity of taint tags. TaintHLS offers a companion high-level synthesis (HLS) methodology to automatically generate such DIFT-enabled accelerators from a high-level specification. We extended a state-of-the-art HLS tool to generate DIFT-enhanced accelerators and demonstrated the approach on numerous benchmarks. The DIFT-enabled accelerators have negligible performance and no more than 30% hardware overhead.

A Uniform Architecture Design for Accelerating 2D and 3D CNNs on FPGAs

Three-dimensional convolutional neural networks (3D CNNs) have gained popularity in many complicated computer vision applications. Many customized accelerators based on FPGAs are proposed for 2D CNNs, while very few are for 3D CNNs. Three-D CNNs are far more computationally intensive and the design space for 3D CNN acceleration has been further expanded since one more dimension is introduced, making it a big challenge to accelerate 3D CNNs on FPGAs. Motivated by the finding that the computation patterns of 2D and 3D CNNs are very similar, we propose a uniform architecture design for accelerating both 2D and 3D CNNs in this paper. The uniform architecture is based on the idea of mapping convolutions to matrix multiplications. A customized mapping module is developed to generate the feature matrix tilings with no need to store the entire enlarged feature matrix on-chip or off-chip, a splitting strategy is adopted to reconstruct a convolutional layer to adapt to the on-chip memory capacity, and a 2D multiply-and-accumulate (MAC) array is adopted to compute matrix multiplications efficiently. For demonstration, we implement an accelerator prototype with a high-level synthesis (HLS) methodology on a Xilinx VC709 board and test the accelerator on three typical CNN models: AlexNet, VGG16, and C3D. Experimental results show that the accelerator achieves state-of-the-art throughput performance on both 2D and 3D CNNs, with much better energy efficiency than the CPU and GPU.

Data-path aware high-level ECO synthesis

Engineering Change Order (ECO) at Register Transfer Level (RTL) has been widely investigated by researchers, but at a higher level of abstraction than RTL, it is not properly addressed. Applying ECO using conventional HLS tools may result in a heavily different RTL in comparison with the original one. In order to minimize this difference, we have proposed a new high-level synthesis methodology, which considers the resulting data-path and its difference from the original one during scheduling and binding of the operations. Experimental results show that our proposed methodology makes only 6.9% changes in the connections of the original data-path in contrast to existing HLS tools, which alter 25.16% of the connections on average. Our methodology exploits 66% less spare cells than the existing HLS tools and makes no change in functional units and registers.

Design space exploration of multi-core RTL via high level synthesis from OpenCL models

As more and more powerful integrated circuits are appearing on the market, more and more applications, with very different requirements and workloads, are making use of available computing power. Designing optimized accelerators that can meet particular requirements has always presented a tremendous challenge to hardware engineers. To do so, designers have to trade off performance for power consumption in a manner such that the final RTL consumes minimum energy to meet the required performance (e.g. FLOPS) target. Moreover, the growing trend towards heterogeneous platforms is crucial to meet time and power consumption constraints of high-performance computing (HPC) applications. The OpenCL parallel programming language and framework enables programming CPU, GPU and recently FPGAs using the high-level synthesis (HLS) methodology. This work presents a design space exploration flow based on execution time, resource utilization and power consumption of OpenCL kernels mapped on FPGAs using the Xilinx high-level synthesis tool chain. Our experiments suggest that the quality of generated solutions, in terms of performance-per-watt, can be determined using analytical formulas prior to implementation, thus enabling fast and accurate DSE by considering on-chip and off-chip sources of parallelism. Moreover, the automated flow suggests design hints to meet a given time constraint within available resources. The proposed technique is demonstrated by optimizing the well known bitonic sorting network from NVIDIA’s OpenCL benchmark. Our results report that FPGAs have at least 20% higher performance-per-watt with respect to two high-end GPUs manufactured in the same technology (28 nm). Additionally, FPGAs with more available resources and using a more modern process (20 nm) can outperform the tested GPUs while consuming at least 55% less power at the cost of more expensive devices.

Spatial and Temporal Redundancy for Transient Fault-Tolerant Datapath

In application specific integrated circuits used in aircraft control systems the effects of transient fault, both in temporal and spatial domain emanating from a single particle strike, cannot be ignored anymore. This is due to scaling of device geometry and surge in frequency. This paper presents novel fault-tolerant high-level synthesis methodology against temporal and spatial impacts of transient at reduced design cost (avg. ∼ 25%) and power (avg. ∼ 48%) than a recent approach.

A Template-Based Design Methodology for Graph-Parallel Hardware Accelerators

Graph applications have been gaining importance in the last decade due to emerging big data analytics problems such as Web graphs, social networks, and biological networks. For these applications, traditional CPU and GPU architectures suffer in terms of performance and power consumption due to irregular communications, random memory accesses, and load balancing problems. It has been shown that specialized hardware accelerators can achieve much better power and energy efficiency compared to the general purpose CPUs and GPUs. In this paper, we present a template-based methodology specifically targeted for hardware accelerator design of big-data graph applications. Important architectural features that are key for energy efficient execution are implemented in a common template. The proposed template-based methodology is used to design hardware accelerators for different graph applications with little effort. Compared to an application-specific high-level synthesis methodology, we show that the proposed methodology can generate hardware accelerators with up to $18\boldsymbol \times$ better energy efficiency and requires less design effort.

Data Transfers Analysis in Computer Assisted Design Flow of FPGA Accelerators for Aerospace Systems

The integration of Field Programmable Gate Arrays (FPGAs) in an aerospace system improves its efficiency and its flexibility thanks to their programmability, but increases the design complexity. The design flows indeed have to be composed of several steps to fill the gap between the starting solution, which is usually a reference sequential implementation, and the final heterogeneous solution which includes custom hardware accelerators. Among these steps, there are the analysis of the application to identify the functionalities that gain advantages in execution on hardware and the generation of their implementations by means of Hardware Description Languages. Generating these descriptions for a software developer can be a very difficult task because of the different programming paradigms of software programs and hardware descriptions. To facilitate the developer in this activity, High Level Synthesis techniques have been developed aiming at (semi-)automatically generating hardware implementations of specifications written in high level languages (e.g., C). With respect to other embedded systems scenarios, the aerospace systems introduce further constraints that have to be taken into account during the design of these heterogeneous systems. In this type of systems explicit data transfers to and from FPGAs are preferred to the adoption of a shared memory architecture. The first approach indeed potentially improves the predictability of the produced solutions, but the sizes of all the data transferred to and from any devices must be known at design time. Identifying the sizes in presence of complex C applications which use pointers can be a not so easy task. In this paper, a semi-automatic design flow based on the integration of an aerospace design flow, an application analysis technique, and High Level Synthesis methodologies is presented. The initial reference application is analyzed to identify which are the sizes of the data exchanged among the different components of the application. Next, starting from the high level specification and from the results of this analysis, High Level Synthesis techniques are applied to automatically produce the hardware accelerators.

Low cost fault tolerance against kc-cycle and km-unit transient for loop based control data flow graphs during physically aware high level synthesis

Recent literatures have proved that current technologies pose grave reliability concern for digital devices due to possibility of multiple (km)-unit transient fault (MTF) and multi (kc)-cycle transient fault (MCT) emanating from particle strike with moderate linear energy transfer (LET). This has arisen due to massive scaling in device dimensions and surge in device frequency happening so far. In the literature solutions for fault tolerant design, that can address MTF and MCT simultaneously during high level synthesis (HLS) for both loop based and non-loop based applications, does not exist. This paper presents the following novel contributions: (a) novel fault tolerant HLS methodology for simultaneously providing multi-cycle (control step) and multi-unit transient fault tolerance for loop based control data flow graphs (b) novel HLS methodology for low cost design solution through exploration of fault tolerant hardware configuration and loop unrolling factor. Results of the proposed approach on standard benchmarks yielded fault tolerant solutions with significantly reduced design cost (average~27%) and power consumption (average~61%) when compared to a recent similar approach.

TL-HLS: Methodology for Low Cost Hardware Trojan Security Aware Scheduling With Optimal Loop Unrolling Factor During High Level Synthesis

Security against hardware Trojan that is capable to change the computational output value is accomplished by employing dual modular redundant (DMR) schedule during high level synthesis (HLS). However, building a DMR for Trojan security is nontrivial and incurs extra delay and hardware. This paper proposes a novel HLS methodology for constraint driven low cost hardware Trojan secured DMR schedule design for loop-based control data flow graphs (CDFGs). Proposed approach simultaneously explores an optimal schedule and optimal loop unrolling factor (U) combination for a low cost Trojan security aware DMR schedule. As a specific example, proposed low cost Trojan secured HLS approach relies on particle swarm optimization algorithm to explore optimized Trojan secured schedule with optimal unrolling that provides security against specific Trojan (causing change in computational output) within user provided area and delay constraints. The novel contributions of this paper are, first an exploration of a low cost Trojan security aware HLS solution for loop-based CDFGs; second, proposed encoding scheme for representing design solution comprising candidate schedule resources, candidate loop unrolling factor and candidate vendor allocation information; third, a process for exploring the a low cost vendor assignment that provides Trojan security; finally, experimental results over the standard benchmark that indicates an average reduction in final cost of ~12% compared to recent approach.

Low‐cost security aware HLS methodology

Owing to massive complexity of modern digital integrated circuits (ICs) disabling complete in-house development, globalisation of the design process establishes itself as an inevitable solution for faster and efficient design. However, globalisation incurs importing intellectual property (IP) cores from various third party vendors, rendering an IP susceptible to hardware threats. To provide trust and security in digital ICs within user constraints, design of a low-cost optimised dual modular redundant, through Trojan secured high-level synthesis (HLS) methodology, is crucial. This study presents exploration of a low-cost optimised HLS solution capable of handling hardware Trojan (providing security) that alters computational output. The key contributions of the study are as: (i) novel low-cost security-aware HLS approach; (ii) novel encoding for representing bacterium in the design space (comprising of candidate datapath resource configuration and vendor allocation information for Trojan secured solution); and (iii) novel exploration process of an efficient vendor allocation procedure that assists in yielding a low-cost Trojan secured schedule. Experimental results indicate significant reduction in the cost of security-aware HLS solution (82.4%) through the proposed approach compared with a recent approach.

Intelligent Custom Block Generation

The current density of integration circuits, yields extremely complex Systems-on-a-Chip (SoCs) that take a long time to design and develop and thus, many times, they miss the market window for these products. This has motivated intensive research on High-level Synthesis (HLS) methodologies, so that such complex and custom systems are rapidly designed and prototyped. The contribution of this work is a formal and intelligent HLS synthesis and rapid verification methodology with custom options, which re-uses and incorporates the generation of predesigned custom hardware functional units, from abstract behavioural ADA code. The usability of the proposed methodology is confirmed with a number of HLS benchmarks including a hierarchical RSA crypto-processor design and a line-drawing algorithm from computer graphics.

Formal ESL Synthesis for Control-Intensive Applications

Due to the massive complexity of contemporary embedded applications and integrated systems, long effort has been invested in high-level synthesis (HLS) and electronic system level (ESL) methodologies to automatically produce correct implementations from high-level, abstract, and executable specifications written in program code. If the HLS transformations that are applied on the source code are formal, then the generated implementation is correct-by-construction. The focus in this work is on application-specific design, which can deliver optimal, and customized implementations, as opposed to platform or IP-based design, which is bound by the limits and constraints of the preexisting architecture. This work surveys and reviews past and current research in the area of ESL and HLS. Then, a prototype HLS compiler tool that has been developed by the author is presented, which utilizes compiler-generators and logic programming to turn the synthesis into a formal process. The scheduler PARCS and the formal compilation of the system are tested with a number of benchmarks and real-world applications. This demonstrates the usability and applicability of the presented method.

High Level Synthesis Design Methodologies for Rapid Prototyping Digital Control Systems

Embedded systems are becoming an important factor of the electronic industry growth due to the higher integration scale of Field Programmable Gate Array (FPGAs). Their designs require high level synthesis (HLS) methodologies to decrease their complexity and design time. In this paper, we discussed a case study of two approaches of HLS design processes approaches. The first one employs Model-Based Design (MBD) flow. The second one uses C-Based Design flow. Both designs were validated on two control drive applications: DC and AC motors. The results indicate the most efficient design methodology.