Abstract
The current density of integration circuits, yields extremely complex Systems-on-a-Chip (SoCs) that take a long time to design and develop and thus, many times, they miss the market window for these products. This has motivated intensive research on High-level Synthesis (HLS) methodologies, so that such complex and custom systems are rapidly designed and prototyped. The contribution of this work is a formal and intelligent HLS synthesis and rapid verification methodology with custom options, which re-uses and incorporates the generation of predesigned custom hardware functional units, from abstract behavioural ADA code. The usability of the proposed methodology is confirmed with a number of HLS benchmarks including a hierarchical RSA crypto-processor design and a line-drawing algorithm from computer graphics.
Highlights
The recent explosion in the density of Integrated Circuits (IC), has caused an amazing proliferation of competitive integrated products in ever reducing lifetime in the market
The source ADA code is transformed into the Intermediate Tables Format (ITF) 2 [3], iiiiiiusing compiler-compiler techniques [4], and ITF is optimally transformed into functionally equivalent hardware using the PARCS (Parallel, Abstract Resource – Constrained Scheduler) optimizer, using logic relations [5], logic predicates and inference logic [6]
SpC is developed within the SUIF compiler environment [8], and the given memory locations are mapped onto variables and arrays in the Verilog modules, which are in turn compiled into hardware circuits using the Synopsys’s Behavioral Compiler
Summary
The recent explosion in the density of Integrated Circuits (IC), has caused an amazing proliferation of competitive integrated products in ever reducing lifetime in the market. Formal High-Level Synthesis (HLS) methodologies are needed, in order to handle this design complexity, achieve higher specification abstraction, development flow automation, quality of implementations and rapid specification-to-product times In this way, enterprises and research organizations will become more competitive and will manage to support customer requirements and short market windows. The source ADA code is transformed into the Intermediate Tables Format (ITF) 2 [3], iiiiiiusing compiler-compiler techniques [4], and ITF is optimally transformed into functionally equivalent hardware using the PARCS (Parallel, Abstract Resource – Constrained Scheduler) optimizer, using logic relations [5], logic predicates and inference logic [6] All these features are integrated into the CCC toolset and methodology and are making possible to automatically generate custom functions and extremely complex custom designs in hardware that can be used to accelerate the host computing system.
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