High-Level Synthesis of Multiclass SVM Using Code Refactoring to Classify Brain Cancer from Hyperspectral Images

Abelardo Baez,Roberto Sarmiento,Samuel Ortega,Francesco Leporati,Himar Fabelo,Gustavo M Callico,Giordana Florimbi,Emanuele Torti,Abian Hernandez,Giovanni Danese

doi:10.3390/electronics8121494

Abelardo Baez, Roberto Sarmiento + Show 8 more

Open Access

https://doi.org/10.3390/electronics8121494

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Abstract

Currently, high-level synthesis (HLS) methods and tools are a highly relevant area in the strategy of several leading companies in the field of system-on-chips (SoCs) and field programmable gate arrays (FPGAs). HLS facilitates the work of system developers, who benefit from integrated and automated design workflows, considerably reducing the design time. Although many advances have been made in this research field, there are still some uncertainties about the quality and performance of the designs generated with the use of HLS methodologies. In this paper, we propose an optimization of the HLS methodology by code refactoring using Xilinx SDSoCTM (Software-Defined System-On-Chip). Several options were analyzed for each alternative through code refactoring of a multiclass support vector machine (SVM) classifier written in C, using two different Zynq®-7000 SoC devices from Xilinx, the ZC7020 (ZedBoard) and the ZC7045 (ZC706). The classifier was evaluated using a brain cancer database of hyperspectral images. The proposed methodology not only reduces the required resources using less than 20% of the FPGA, but also reduces the power consumption −23% compared to the full implementation. The speedup obtained of 2.86× (ZC7045) is the highest found in the literature for SVM hardware implementations.

Highlights

High-level synthesis (HLS) methodologies allow hardware (HW) designers to increase the abstraction level and accelerate the automation for the synthesis and verification of the design process.The current rise in the complexity of the applications and the increment of the capabilities of silicon technologies, as well as the so called time to market constrain, make high-level synthesis (HLS) methodologies and tools of mandatory use in the near future [1]
For readers who are interested in different implementations using diverse devices and including a training implementation and a classification one, we recommend [12], where the authors review the state-of-arts of support vector machine (SVM) implementations using different types of field programmable gate arrays (FPGAs)
The results obtained in this work demonstrate the major benefits of writing efficient code for HLS tools, in this case SDSoC, to accelerate a binary SVM classifier

Summary

Introduction

High-level synthesis (HLS) methodologies allow hardware (HW) designers to increase the abstraction level and accelerate the automation for the synthesis and verification of the design process.The current rise in the complexity of the applications and the increment of the capabilities of silicon technologies, as well as the so called time to market constrain, make HLS methodologies and tools of mandatory use in the near future [1]. Some implementations of support vector machine (SVM) classifiers in field programmable gate arrays (FPGAs) have been released in different applications, such as image processing [5,6], Electronics 2019, 8, 1494; doi:10.3390/electronics8121494 www.mdpi.com/journal/electronics. Electronics 2019, 8, 1494 automotive [7], medical [8,9], and data signal processing [10,11], among others. These implementations use different platforms depending on the application and the desired accuracy and timing. The dataset employed is based on traditional RGB (red, green, and blue) images and the generation of a binary SVM model, having an output of the class as 1

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