Abstract

Engineering Change Order (ECO) at Register Transfer Level (RTL) has been widely investigated by researchers, but at a higher level of abstraction than RTL, it is not properly addressed. Applying ECO using conventional HLS tools may result in a heavily different RTL in comparison with the original one. In order to minimize this difference, we have proposed a new high-level synthesis methodology, which considers the resulting data-path and its difference from the original one during scheduling and binding of the operations. Experimental results show that our proposed methodology makes only 6.9% changes in the connections of the original data-path in contrast to existing HLS tools, which alter 25.16% of the connections on average. Our methodology exploits 66% less spare cells than the existing HLS tools and makes no change in functional units and registers.

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