Real-time energy-efficient software and hardware implementations of a QCSP communication system

Abstract

In the Internet of Things, the energy efficiency of communications is crucial. Thus, using data-less preambles to detect frames is suboptimal. A preamble-less physical layer named “Quasi-Cyclic Short Packet (QCSP)” proposed a solution. However, the high computational complexity of the receiver makes the implementation challenging. This paper studies the feasibility and efficiency of real-time software and hardware QCSP systems. Several highly efficient transmitter implementations are presented, demonstrating the relevance of the approach. The parallelization and optimization strategies are elaborated for both software and hardware receiver implementations. They allowed software implementations with throughputs above 50 kb/s (maximum for the LoRa standard), consuming as low as 27 μJ/b. Thanks to detailed algorithm refinements, the throughtput even exceeded 250 kb/s on FPGA using High-Level Synthesis methodology, for an estimated consumption of 3.9 μJ/b. The results support the viability of the QCSP approach for cloud-RAN and edge computing in Low-Power Wide-Area Networks.