Gate Tunneling Current Research Articles

Investigation of gate leakage current in TFET: A semi-numerical approach

Tunneling FET (TFET) has been demonstrated as a favorable candidate to replace conventional MOSFETs in low-power applications. However, there are many challenges that should be overcome to efficiently operate the TFET. One of the most limiting factors that can restrict the TFET performance is the gate leakage current. In this paper, the tunneling leakage current through the gate oxide of double gate TFET has been analyzed. The conduction band energy level for gate-oxide-silicon was employed to calculate the tunneling transmission coefficient by utilizing a numerical method. To obtain the potential barrier between the gate and the channel surface, a modified analytical pseudo-2D method has been applied to deduce the corresponding surface potential taking into account a precise calculation of depletion regions. Furthermore, the inclusion of the image charge barrier lowering effect is incorporated in calculating the transmission probability through the oxide. Including such an effect shows a significant influence on determining the gate tunneling current. The gate leakage current has been calculated for various bias voltages and equivalent oxide thicknesses. The presented semi-numerical technique shows good agreement within a suitable CPU time when validated and compared against full numerical TCAD simulation.

Modeling of the Gate Tunneling Current in MFIS NCFETs

In this article, we present a model for the gate tunneling current (GTC) in metal-ferroelectric-insulator-semiconductor (MFIS) negative capacitance FETs (NCFETs), which, to the best of our knowledge, is the first such report. The model is numerical in nature, and is developed using the Tsu–Esaki formulation, employing the Wentzel–Kramer–Brillouin (WKB) approximation, in order to estimate the transmission coefficients of the carriers through the barriers. The ferroelectric (FE) material considered is HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> , and is modeled using the Landau phase transition theory. Simulation results reveal a remarkable nonmonotonic dependence of the GTC on the FE layer thickness, an effect that we explain through the Landau model. Furthermore, it is shown how this GTC can be reduced by orders of magnitude without changing the overall dielectric capacitance—a feature that may prove to be beneficial in low-power circuit designs. Additionally, it is seen that the GTC is a weak function of the remanent polarization and coercive field of the FE. All the model predictions are validated through a comparison with the results obtained from Sentaurus 2-D TCAD simulations. The novel results presented in this work should serve as a guide for detailed experimental studies on the gate current characteristics of MFIS NCFETs.

Unified Model of Shot Noise in the Tunneling Current in Sub-10 nm MOSFETs.

A single unified analytical model is presented to predict the shot noise for both the source-to-drain (SD) and the gate tunneling current in sub-10 nm MOSFETs with ultrathin oxide. Based on the Landauer formula, the model is constructed from the sequential tunneling flows associated with number fluctuations. This approach provides the analytical formulation of the shot noise as a function of the applied voltages. The model performs well in predicting the Fano factor for shot noise in the SD and gate tunneling currents.

Physics-Informed Neural Network for High Frequency Noise Performance in Quasi-Ballistic MOSFETs

A physics-informed neural network (PINN) model is presented to predict the nonlinear characteristics of high frequency (HF) noise performance in quasi-ballistic MOSFETs. The PINN model is formulated by combining the radial basis function-artificial neural networks (RBF-ANNs) with an improved noise equivalent circuit model, including all the noise sources. The RBF-ANNs are utilized to model the thermal channel noise, induced gate noise, correlation noise, as well as the shot noise, due to the gate and source-drain tunneling current through the potential barriers. By training a spatial distribution of the thermal channel noise and a Fano factor of the shot noise, underlying physical theories are naturally embedded into the PINN model as prior information. The PINN model shows good capability of predicting the noise performance at high frequencies.

A compact model for gate tunneling currents in undoped cylindrical surrounding-gate metal-oxide-semiconductor field-effect transistors

We present a compact model of the gate tunneling current in cylindrical surrounding-gate (SG) metal-oxide-semiconductor field-effect transistors (MOSFETs) based on quantum mechanical correction. The model is physics-based and is given in an analytical closed form. We start by deriving a quadratic approximation of the quantum electrostatic potential with the two lowest energy levels using quantum perturbation theory. In addition, small-diameter cylindrical SG MOSFETs can be described excellently by taking both structural and electrical confinement effects into account. A self-consistent Schrödinger-Poisson simulation was used as a benchmark to assess the proposed model. It was found that the calculated gate tunneling currents determined using the model matched well with the corresponding currents derived using self-consistent calculations. The model is thus useful for fast analysis of gate tunneling currents within the context of a circuit simulator.

Theoretical analysis and optimization of high-k dielectric layers for designing high-performance and low-power-dissipation nanoscale double-gate MOSFETs

The carrier transport and tunneling mechanisms in nanoscale double-gate metal–oxide–semiconductor field-effect transistors (MOSFETs) with different dielectric layers is investigated using a simple two-dimensional analytical model, revealing good agreement with drift–diffusion and hydrodynamic models at lower gate voltages. The model is utilized to optimize the MOSFET performance by minimizing the carrier leakage and improving the gate control on the carrier transport through the channel, which can be determined by the gate-to-drain capacitance ratio. It is well known that thicker physical layers of high-k dielectrics can be used to reduce the gate tunneling current without compromising the gate controllability over the channel conduction, by providing the same equivalent oxide thickness as SiO2. However, use of a dielectric layer with a lower conduction-band offset (CBO) in a Si MOSFET can result in appreciable tunneling through the gate, as shown in our computational results for the TiO2 layer. In this study, we obtain an optimized thickness of 10 A for the La2O3 dielectric layer, which results in a minimum leakage current via tunneling and a maximum gate-to-drain capacitance ratio due to its high dielectric constant and CBO. Such devices could be applicable in analog amplifier circuits due to their high intrinsic gain and lower “on” and “off” static power dissipation. The analysis of this device in a digital circuit also shows a higher Ion/Ioff ratio with the least drain-induced barrier lowering effect. The results of this study thus predict the suitability of this MOSFET for use in low-power devices and logic circuits.

Various Issues and considerations for the Static Power Consumption in NANO-CMOS: Design Perspective

Now a days designing techniques are very much concerned about the leakage currents reduction at different stages of abstraction.Leakage reduction strategies can be categorized on the basis of their effectiveness and output rate of 3 major classes: enhanced devices, trade off techniques, and leakage management. Static power consumption by the leakage currents is the main issue in CMOS ICs with gate lengths of 90 nm and less than that. Generally, the procedure allied with deviation may extensively amplify the whole amount of static current usage rate. The prime sources of variability are changes in: (i) changes in channel dimensions, (ii) changes in oxide thickness (iii) changes in channel doping profiles. Channel aspect of transistor in profound submicron technologies are subjected to the “classical” optical resolution bound. The 90 nm or 65 nm channel length is defined with wavelength of lower UV of 193 nm (or 157 nm). Static current expenditure has turn out to be extremely significant issue for the developers of lower submicron CMOS process and for designers of circuits. As the length of gate and threshold voltage reduces the subthreshold drain current rises significantly. Other components of the total static current consumption, such as gate tunneling currents, also come into existence. These issues have been covered in this work very effectively from designing perspective

Accurate modeling of gate tunneling currents in Metal-Insulator-Semiconductor capacitors based on ultra-thin atomic-layer deposited Al2O3 and post-metallization annealing

Even though the introduction of high-dielectric constant (high-κ) materials has enabled the continuous advancement of Moore's Law into the nanometer regime, accurate predictions ensuring long-term operation of these devices is now more complicated due to several physical and electronic considerations: 1) precise atomic control of the high-k material in the ultra-thin regime (thickness, stoichiometry, dielectric constant, etc.), 2) excessively large gate leakage currents, 3) appearance of several conduction mechanisms able to degrade the performance and reliability of the devices, 4) interfacial defects at the high-k/silicon interface and 5) low thermodynamic stability of the high-k materials after exposure to inherent thermal treatments during several processing stages. In order to provide better device performance/reliability predictions, this work offers a consistent and accurate verification of the precise carrier conduction mechanisms of Metal-Insulator-Semiconductor (MIS) capacitors (biased under substrate injection conditions) when ultra-thin Al2O3 films (5 and 10nm in thickness and deposited by thermal atomic-layer deposition) are used as the gate oxide before and after a post-metallization annealing in a H2/N2 atmosphere. From experimental Current-Voltage data of these MIS devices, along with the use of SILVACO simulations and well established semi-empirical models, the precise conduction mechanisms as well as important physical and electronic parameters (consistent with the conduction models) were extracted. We show that even though an H2-based anneal is able to passivate silicon dangling bonds, gate leakage current for Al2O3 increases while keeping the same conduction models thus offering clues for better reliability predictions before failure.

Influence of -ray total dose radiation effect on the tunneling gate current of the uniaxial strained Si nanometer n-channel metal-oxide-semiconductor field-effect transistor

The carrier microscopic transport process of uniaxial strained Si n-channel metal-oxide-semiconductor field-effect transistor (NMOSFET) is analyzed under -ray radiation. The model of radiation-induced defect densities that are quantitative representations of trapped charges integrated across the thickness of the oxide (Not), and the number of interface traps at the semiconductor/oxide interface (Nit), is established. The variations of electrical characteristics of the uniaxial strained Si nanometer NMOSFET are also investigated under the total dose radiation. The device of uniaxial strained Si nanometer NMOSTET is irradiated by a 60Co -ray laboratory source at a constant dose rate of 0.5 Gy (Si)/s. The TID is deposited in several steps up to a maximum value of 2.5 kGy. Electrical measurements are performed at each TID step. All irradiated samples are measured using field test, and are required to finish measurement within 30 min, in order to reduce the annealing effect. Static drain-current ID vs. gate-voltage VGS electrical characteristics are measured with an HP4155B parametric analyzer. Some parameter extractions presented here come from these static measurements including the threshold voltage VTH, the trans-conductance gm, and the leakage current IOFF (ID at VGS=0 V and VDS=VDD). Irradiation bias:VG=+1 V, drain voltage VD is equal to source voltage VS (VD=VS=0). Measurement bias:VG=0-1 V, scanning voltage Vstep=0.05 V, VD=50 mV, and VS=0. The results indicate the drift of threshold voltage, the degradation of carrier mobility and the increase of leakage current because of the total dose radiation. Based on quantum mechanics, an analytical model of tunneling gate current of the uniaxial strained Si nanometer is developed due to the total dose irradiation effect. Based on this model, numerical simulation is carried out by Matlab. The influences of total dose, geometry and physics parameters on tunneling gate current are simulated. The simulation results show that when radiation dose and bias are constant, the tunneling gate current increases as the channel length decreases. When the structure parameters and the stress are fixed, the tunneling gate current increases with the increase of radiation dose. Whereas at a given the radiation dose, tunneling gate current will decrease due to the stress. When radiation dose and bias are kept unchanged, the tunneling gate current increases with the thickness of the gate oxide layer decresing. When the gate-source voltage, the thickness of oxide layer and stress are fixed, tunneling gate current is reduced with the increase of doping concentration in channel. When the structural parameters, the gate-source voltage and radiation dose are constant, the tunneling gate current decreases with increasing drain-source voltage. In addition, to evaluate the validity of the model, the simulation results are compared with experimental data, and good agreement is confirmed. Thus, the experimental results and proposed model provide good reference for research on irradiation reliability and application of strained integrated circuit of uniaxial strained Si nanometer n-channel metal-oxide-semiconductor field-effect transistor.

The Influence of High-k Material/SiO&lt;sub&gt;2&lt;/sub&gt; Gate Stacks on Direct Gate Tunneling Current of Cylindrical Surrounding-Gate MOSFETs

In this paper, we present a model of gate tunneling current in cylindrical surrounding-gate MOSFETs through dual layer high-k dielectric/SiO2 stacks. The model was derived under a quantum perturbation theory by taking into account both structural and electrical confinement effects. The influences of high-k materials and SiO2 thickness on the gate tunneling current have been studied. The calculated results show that the HfO2 is the most effective high-k material to decrease the gate tunneling current. It is also shown that the gate tunneling current is reduced with the SiO2 thickness. In addition, the obtained tunneling currents are fitted well with those obtained under the self-consistent calculation.

Transistor and pin reordering for leakage reduction in CMOS circuits

Leakage power is currently a critical problem in nanometer-scale CMOS circuit technology. In this paper, a novel reordering method for reducing the overall leakage currents is proposed for CMOS logic gates, including CMOS complex gates. This new method takes into account the subthreshold leakage current (ISUB) and gate leakage current (IG) and includes the often-ignored reverse gate tunneling current (IRG). Additionally, this method considers the interaction between leakage components based on the stacking/non-stacking effect case and different W/L ratios of an on-/off-transistor block in a stack. Thus, unlike existing approaches, the proposed method can generate the best configuration for leakage reduction even in CMOS complex gates, and can be used in combination with other leakage reduction techniques to achieve further improvement.

Direct tunneling gate current model for symmetric double gate junctionless transistor with SiO2/high-k gate stacked dielectric

A junctionless transistor is emerging as a most promising device for the future technology in the decananometer regime. To explore and exploit the behavior completely, the understanding of gate tunneling current is of great importance. In this paper we have explored the gate tunneling current of a double gate junctionless transistor (DGJLT) for the first time through an analytical model, to meet the future requirement of expected high-k gate dielectric material that could replace SiO2. We therefore present the high-k gate stacked architecture of the DGJLT to minimize the gate tunneling current. This paper also demonstrates the impact of conduction band offset, workfunction difference and k-values on the tunneling current of the DGJLT.

Analytical Model of Tunneling Current by High Dielectrics and Study of High-k Gate Stack Structure

With the persistent scale of dielectrics through scaling technology towards the nanoscale method and a precise model of tunnel current becomes important as well as essential to understand the scaling limits. While precised by (ITRS) and elevated presentation CMOS circuit has the utmost current density limit for 90 nm skill nodes. Below 2nm oxide tunneling current becomes difficult. Classical physics is not enough to explain the device physics at nanoscale. So a quantum mechanical study becomes essential to provide thorough evaluation of the device behavior at nanoscale. By solving Schrodinger Equation, analytical model for gate tunneling current has been urbanized using (WKB) approximation method. The tunneling current has been calculated for direct tunneling from channel to gate for both electrons and holes. To avoid the problem of gate tunneling current below 90 nm or we can say that at 65 nm and 45 nm another gate dielectric material is used that has high dielectric constant than SiO2. Three gate dielectric materials Si3N4, HfO2, Al2O3 has been deliberated .All the three gate dielectrics are used to scale down the thickness of oxide ranging from 1.42 nm to 0.96 nm. Results have been compared with the numerical model and also with the semi-empirical model.

Leakage current of germanium-on-insulator-based junctionless nanowire transistors

Junctionless nanowire transistors (JNTs) have been fabricated on ultra-thin-body germanium-on-insulator (GOI) substrates using a simple Si-compatible top-down process. These JNTs, which have gate lengths and widths that are both less than 100 nm, exhibit good electrical characteristics (Ion/Ioff ratio of ∼105 at Vd = −1 V). The effects of the back gate voltage, temperature, the device dimensions, and the channel doping concentration on the leakage currents of the fabricated devices were experimentally analyzed in detail. The results indicate that the leakage current is mainly affected by the gate tunneling current, the Shockley-Read-Hall generation current, the band-to-band tunneling current and the trap-assisted tunneling current. Design guidelines were then proposed to reduce the leakage currents of GOI-based JNTs.

Gate Tunnelling Current Model for Nanoscale MOSFETs with Varying Surface Potential

ABSTRACTAt nanoscale, the channel of metal oxide semiconductor field effect transistors (MOSFETs) acts like a potential well within which electron energy levels are quantized and a nonzero wavefunction is obtained at the oxide–semiconductor interface. As a result the gate tunnelling current has emerged a significant constraint in respect of scaling of ultrathin gate oxides. We have developed an analytical model considering varying surface potential with applied voltage for evaluating gate tunnelling current through thin dielectrics in nanoscale MOSFETs. The electron wavefunction has been calculated by treating the band profile in the channel as a triangular potential well. The tunnelling probability through the gate oxide has been evaluated using Jeffreys–Wentzel–Kramers–Brillouin approximation method. The tunnelling current density is estimated from the evaluated interface wavefunction along with the tunnelling probability. The results from the present model compare well with the published Mondal–Dutta model and the experimental data. The novelty of the present model lies in its simplicity and its analyticity requiring much less computational efforts for its implementation.

Thermo-Magnetic Effects in Nano-Scaled MOSFET: An Experimental, Modeling, and Simulation Approach

A numerical simulation methodology for incorporating thermo-magnetic effects on the MOSFET gate tunneling current is introduced. The methodology is based on the solution of the Schrödinger-Poisson coupled system, which allows simulating the influence of a static magnetic field and temperature on the wave functions and gate tunneling current of MOSFET devices. In addition to the preliminary results on the simulation methodology, experimental results on the effect of the magnetic field on the subthreshold slope, the off-current, and transconductance, are also introduced. The proposed simulation methodology, in conjunction with experimental data, is useful for device degradation and reliability studies in nano-scaled MOSFET devices. This experimental characterization technique sets also the basis for the development of a magnetic force nanoscopy technique, where the conductive properties, thanks to the Lorentz force, can be two-dimensionally mapped over the nano-scaled MOSFET channel plane.

Analytical modeling of the direct tunneling current through high-k gate stacks for long-channel cylindrical surrounding-gate MOSFETs

An analytical direct tunneling gate current model for cylindrical surrounding gate (CSG) MOSFETs with high-k gate stacks is developed. It is found that the direct tunneling gate current is a strong function of the gate's oxide thickness, but that it is less affected by the change in channel radius. It is also revealed that when the thickness of the equivalent oxide is constant, the thinner the first layer, the smaller the direct tunneling gate current. Moreover, it can be seen that the dielectric with a higher dielectric constant shows a lower tunneling current than expected. The accuracy of the analytical model is verified by the good agreement of its results with those obtained by the three-dimensional numerical device simulator ISE.

Gate Tunneling Current Predicting Model for Scaled NMOSFET Devices

With the scaling of MOS devices, gate tunneling current increases significantly due to thinner gate oxides, and static characteristics of devices and circuit are severely affected by the presence of gate tunneling currents. In this paper, a novel theory gate tunneling current predicting model using integral approach is presented in ultra-thin gate oxide MOS devices that tunneling current changes with gate-oxide thickness. To analyze quantitatively the behaviors of scaled MOS devices in the effects of gate tunneling current and predict the trends, the characteristics of MOS devices are studied in detail using HSPICE simulator. The simulation results in BSIM4 model well agree with the model proposed. The theory and experiment data are contributed to the VLSI circuit design in the future.

Surface Potential Based Analytical Modeling of Double Gate MOSFET with Si and Au Nano-Dots Embedded Gate Dielectric for Non-Volatile Memory Applications

In this paper we present an analytical study of Double Gate (DG) MOSFET memory devices with Si and Au nanocrystal embedded gate dielectric stacks. We considered an undoped long channel DG MOSFET, having a multilayer SiO2 (5 nm)–Si/Au nc embedded Si3N4 (6 nm)–SiO2 (7 nm) gate dielectric. From a quasi-1-D analytic solution of the Poisson equation, the potential and the electric fields in the substrate and the different layers of the gate oxide stack were derived. Thereafter following a trap-like model using the WKB approximation, we have investigated the Fowler Nordheim tunneling currents from the Si inversion layer to the embedded nanocrystal states in such devices. We evaluated the write-erase characteristics, gate tunneling currents, threshold voltage shifts and the output characteristics of the NVM devices from our analytical model. The performance of the nanoparticle embedded DGMOS memory device was compared with that of a DG SONOS NVM of similar dimensions. From the studies, the nc embedded devices showed better performance than the conventional SONOS DGMOS NVM. Among the two ncs compared the nc-Au embedded device emerged as the better performer in terms of higher charge density, faster charging, higher threshold voltage shift and better charge retention.

Analytical Model for Direct Tunneling Gate Current in Long-Channel Undoped Cylindrical Surrounding Gate Metal–Oxide–Semiconductor Field Effect Transistors

In this study, an analytical direct tunneling gate current model for long-channel undoped cylindrical surrounding gate (CSG) MOSFETs is developed. On the basis of an analytical model, the direct tunneling gate current in CSG MOSFETs is investigated. It is found that direct tunneling gate current is a strong function of gate oxide thickness, but less affected by the change in channel radius. It is also revealed that considering the influence of the source and drain, as the length of the underlap region decreases to zero, the direct tunneling gate current drastically increases. The accuracy of the analytical model is verified by the good agreement of its results with those obtained by the three-dimensional numerical device simulator ISE.