Analytical Model of Tunneling Current by High Dielectrics and Study of High-k Gate Stack Structure

Abstract

With the persistent scale of dielectrics through scaling technology towards the nanoscale method and a precise model of tunnel current becomes important as well as essential to understand the scaling limits. While precised by (ITRS) and elevated presentation CMOS circuit has the utmost current density limit for 90 nm skill nodes. Below 2nm oxide tunneling current becomes difficult. Classical physics is not enough to explain the device physics at nanoscale. So a quantum mechanical study becomes essential to provide thorough evaluation of the device behavior at nanoscale. By solving Schrodinger Equation, analytical model for gate tunneling current has been urbanized using (WKB) approximation method. The tunneling current has been calculated for direct tunneling from channel to gate for both electrons and holes. To avoid the problem of gate tunneling current below 90 nm or we can say that at 65 nm and 45 nm another gate dielectric material is used that has high dielectric constant than SiO2. Three gate dielectric materials Si3N4, HfO2, Al2O3 has been deliberated .All the three gate dielectrics are used to scale down the thickness of oxide ranging from 1.42 nm to 0.96 nm. Results have been compared with the numerical model and also with the semi-empirical model.