Theoretical analysis and optimization of high-k dielectric layers for designing high-performance and low-power-dissipation nanoscale double-gate MOSFETs

Abstract

The carrier transport and tunneling mechanisms in nanoscale double-gate metal–oxide–semiconductor field-effect transistors (MOSFETs) with different dielectric layers is investigated using a simple two-dimensional analytical model, revealing good agreement with drift–diffusion and hydrodynamic models at lower gate voltages. The model is utilized to optimize the MOSFET performance by minimizing the carrier leakage and improving the gate control on the carrier transport through the channel, which can be determined by the gate-to-drain capacitance ratio. It is well known that thicker physical layers of high-k dielectrics can be used to reduce the gate tunneling current without compromising the gate controllability over the channel conduction, by providing the same equivalent oxide thickness as SiO2. However, use of a dielectric layer with a lower conduction-band offset (CBO) in a Si MOSFET can result in appreciable tunneling through the gate, as shown in our computational results for the TiO2 layer. In this study, we obtain an optimized thickness of 10 A for the La2O3 dielectric layer, which results in a minimum leakage current via tunneling and a maximum gate-to-drain capacitance ratio due to its high dielectric constant and CBO. Such devices could be applicable in analog amplifier circuits due to their high intrinsic gain and lower “on” and “off” static power dissipation. The analysis of this device in a digital circuit also shows a higher Ion/Ioff ratio with the least drain-induced barrier lowering effect. The results of this study thus predict the suitability of this MOSFET for use in low-power devices and logic circuits.