Accurate modeling of gate tunneling currents in Metal-Insulator-Semiconductor capacitors based on ultra-thin atomic-layer deposited Al2O3 and post-metallization annealing

Abstract

Even though the introduction of high-dielectric constant (high-κ) materials has enabled the continuous advancement of Moore's Law into the nanometer regime, accurate predictions ensuring long-term operation of these devices is now more complicated due to several physical and electronic considerations: 1) precise atomic control of the high-k material in the ultra-thin regime (thickness, stoichiometry, dielectric constant, etc.), 2) excessively large gate leakage currents, 3) appearance of several conduction mechanisms able to degrade the performance and reliability of the devices, 4) interfacial defects at the high-k/silicon interface and 5) low thermodynamic stability of the high-k materials after exposure to inherent thermal treatments during several processing stages. In order to provide better device performance/reliability predictions, this work offers a consistent and accurate verification of the precise carrier conduction mechanisms of Metal-Insulator-Semiconductor (MIS) capacitors (biased under substrate injection conditions) when ultra-thin Al2O3 films (5 and 10nm in thickness and deposited by thermal atomic-layer deposition) are used as the gate oxide before and after a post-metallization annealing in a H2/N2 atmosphere. From experimental Current-Voltage data of these MIS devices, along with the use of SILVACO simulations and well established semi-empirical models, the precise conduction mechanisms as well as important physical and electronic parameters (consistent with the conduction models) were extracted. We show that even though an H2-based anneal is able to passivate silicon dangling bonds, gate leakage current for Al2O3 increases while keeping the same conduction models thus offering clues for better reliability predictions before failure.