Various Issues and considerations for the Static Power Consumption in NANO-CMOS: Design Perspective

Abstract

Now a days designing techniques are very much concerned about the leakage currents reduction at different stages of abstraction.Leakage reduction strategies can be categorized on the basis of their effectiveness and output rate of 3 major classes: enhanced devices, trade off techniques, and leakage management. Static power consumption by the leakage currents is the main issue in CMOS ICs with gate lengths of 90 nm and less than that. Generally, the procedure allied with deviation may extensively amplify the whole amount of static current usage rate. The prime sources of variability are changes in: (i) changes in channel dimensions, (ii) changes in oxide thickness (iii) changes in channel doping profiles. Channel aspect of transistor in profound submicron technologies are subjected to the “classical” optical resolution bound. The 90 nm or 65 nm channel length is defined with wavelength of lower UV of 193 nm (or 157 nm). Static current expenditure has turn out to be extremely significant issue for the developers of lower submicron CMOS process and for designers of circuits. As the length of gate and threshold voltage reduces the subthreshold drain current rises significantly. Other components of the total static current consumption, such as gate tunneling currents, also come into existence. These issues have been covered in this work very effectively from designing perspective