Gate Tunnel Field Effect Transistor Research Articles

An analytical approach of elimination of ambipolarity of DPDG- TFET using strained type II staggered SiGeSn heterostructure

The effect of ambipolarity puts TFET in an unfavorable position and restricts its superiority. The inclusion of a drain pocket at the drain-channel junction can prove it to be a realistic and successful way to remove the ambipolarity completely. In this paper, a 2-D analytical model has been presented for a Drain Pocket Double Gate Tunnel Field Effect Transistor (DP DG-TFET). The theoretical model agrees well with the previously reported data of Si DP DG-TFET. In this work, the SiGeSn heterostructure is used to achieve a lower bandgap and therefore to improve the tunnelling probability. A high ON current without any ambipolarity can be achieved from such type of DP DG-TFET.

Source pocket engineered underlap stacked-oxide cylindrical gate tunnel FETs with improved performance: design and analysis

The effects of stacked SiO2/HfO2 gate oxide, source pocket, and underlap gate engineering on the electrical and RF performances of cylindrical gate tunnel field-effect transistors (CGTFETs) have been investigated in this paper. While source pocket with underlap engineering reduces both the gate leakage current and subthreshold swing (SS), the stacked gate oxide improves the drain current of the CGTFET. The DC and RF performance parameters such as the electric field, drain current, transconductance, gate capacitance, unity gain cut-off frequency, gain–bandwidth product, transconductance frequency product, and intrinsic delay have been investigated for different stacked oxide CGTFETs with and without a source pocket as well as with and without an underlap structure. Our study demonstrates that the proposed underlapped stacked-oxide source-pocket engineered CGTFET structure not only enhances the drain current, but also improves the subthreshold switching characteristics of the device by reducing SS and gate leakage current.

Numerical analysis of Mg2Si/Si heterojunction DG-TFET for low power/high performance applications: Impact of non- idealities

Abstract In the advanced technology nodes, conventional MOSFETs are being replaced by tunnel field effect transistors (TFETs), due to its potential of achieving subthreshold swing (SS) less than 60 mV/decade. However, certain constraints are to be met to improve the performance of TFET in terms of higher ON current (ION) and lower threshold voltage (Vth). Here, in this paper, magnesium silicide/silicon (Mg2Si/Si) heterojunction double gate TFET (Mg2Si/Si HDG-TFET) is explored and is simultaneously compared with conventional silicon double gate TFET (Si DG-TFET). Results depict superior performance of Mg2Si/Si HDG-TFET as compared to conventional Si DG-TFET, in terms of dc characteristics, i.e., ION, Vth, SS, and ION/IOFF ratio. Obtained Vth (0.26 V), SS (10.05mV/decade) and ION/IOFF ratio (1013) for the case of Mg2Si HDG-TFET shows an improvement of 77%, 49% and 10 decades respectively compared to counterpart i.e., Si DG-TFET. In particular, this improvement in the performance of Mg2Si/Si HDG-TFET over Si DG-TFET is attributed to staggered type-II heterojunction interface at the source-channel junction, which leads to reduction of the width for interband tunneling barrier and hence, improves ION. This viability of the device is also determined by analyzing the impact of non-idealities present in the device. In this respect, the Gaussian and tail defects are considered in the bulk of Mg2Si. The results reveal that the Gaussian defects alter the device characteristics mainly in the subthreshold regime, whereas, in the ON state, the impact of defects is minimal. Further, it is obtained that the device is much immune for tail defects in comparison with the Gaussian defects. The CV analysis reveals a marginal degradation in parasitic capacitances for Mg2Si/Si HDG-TFET as compared to Si DG-TFET. However, this degradation can be overlooked against the remarkably enhanced drain current. Thus, the device overcomes the bottleneck of TFET and provides high ION and low Vth without degrading the other performance parameters and hence is suitable for low power analog and digital applications.

Effect of temperature on analog performance of Mg2Si source heterojunction double gate tunnel field effect transistor

Tunnel field effect transistor (TFET) has been recognized as a better candidate to replace Metal Oxide Semiconductor Field Effect Transistor (MOSFET) owing to its competence to achieve subthreshold swing (SS) less than 60 mV/decade and to reduce short channel effects (SCEs). However, certain limitations (low ON current and ambipolar conduction) need to be overcome so as to enhance the performance of TFET. In this paper, source material engineering (SME) is investigated to enhance ION, by replacing the material of the source region of conventional silicon double gate (DG) TFET by a low bandgap material Magnesium Silicide (Mg2Si). It is observed from simulation results that with Mg2Si as a source presented superior performance with reference to ION, Vth, SS, and ION/IOFF ratio as compared to the conventional Si DG-TFET. Further, reliability issues related to the temperature affectability for the electrical/analog performance of the proposed device is investigated for ambient temperature range (200 K to 400 K). The study done for temperature affectability reveals that, Shockley–Read–Hall recombination dominates in the subthreshold region and band to band tunneling (BTBT) mechanism is dominant in superthreshold region. Furthermore, as temperature is elevated from 200 K to 400 K, IOFF shows significant degradation by an order of 106. Also, it is evident that with increase in temperature threshold voltage (Vth) decreases and transconductance (gm) increases. This study will be helpful in achieving the better performance for Mg2Si source DG-TFET implemented in analog applications.

Analytical Current Transport Modeling of Monolayer Molybdenum Disulfide-Based Dual Gate Tunnel Field Effect Transistor

In this paper, we present a current transport model of MoS2-based dual gate tunnel field effect transistor from both analytical and numerical techniques. In analytical modeling, two-dimensional (2D) model of potential distribution with its corresponding energy level for the hetero-junction has been solved and implemented with Landauer current transport mechanism. The output characteristics have been compared with the quantum mechanical solution obtained from non-equilibrium Green's function (NEGF) formalism. The sub-threshold slope (SS), obtained from analytical and NEGF methods are 10 mV/decade and 12.6 mV/decade with on/off current ratio of 107 and 106, respectively at VDS = 0.5 V. We have considered scattering mechanism into our calculation and have shown that carrier transportation for 20 nm channel length is diffusive. In addition, scattering reduces the on current by an order of magnitude, and resembles good agreement with the atomistic simulation. Lastly, mobility and ionized impurity concentration for our proposed structure have been calculated as 27.2 cm2/Vs and 1.17 × 1013/cm2.

Enhancement of Performance in TFET by Reducing High-K Dielectric Length and Drain Electrode Thickness

A Dual Material Double Gate Tunnel Field Effect Transistor (DMDGTFET) with reduced high-K dielectric length (LK = 15 nm) and drain electrode thickness (6 nm) is proposed and performed a TCAD simulation. The simulation result of proposed device exhibits suppression in gate-to-drain capacitance (CGD). The (CGD) is proportional to dielectric constant (e) of the gate insulator and drain-electrode thickness of device. In the proposed DMDGTFET, the reduction in drain electrode thickness and LK gives a low electron concentration (Q) and low dielectric constant (e) in channel/drain junction, respectively, which results in suppression of CGD. At VGS = 2 V, the CGD for the proposed and conventional device are 9 f F, and 7 f F, respectively. In addition, the proposed device exhibit unity current-gain cut-off frequency of 62 GHz, while it is 57 GHz for conventional device. The on-current (ION) of the proposed device is also measured as 2 × 10−5 (A/mm). Thus, the proposed DMDGTFET is potential candidate for fast switching applications without compromising on-current (ION).

Comparative Analyses of Circular Gate TFET and Heterojunction TFET for Dielectric-Modulated Label-Free Biosensing

This paper compares circular gate (CG) tunnel field effect transistor (TFET) and uniform gate Heterojunction (HJ) TFET as label-free biosensors based on dielectric modulation. Neutral and charged biomolecules with different values of dielectric constant are considered. Sensitivities of partially filled nanogaps arising out of steric hindrance in both the biosensors for concave, convex, increasing and decreasing step profiles of biomolecules are compared. The effect of probe position on sensitivities of the two biosensors is reported for various cases. A status map is presented, plotting the sensitivities of some of the most significant works in applications of FET as label-free biosensors along with sensitivities of the proposed devices. CG TFET exhibits higher sensitivity than HJ TFET due to its non-uniform gate architecture. The sensitivities of the TFETs are highly dependent on the position of biomolecules (steric hindrance and probe position) with respect to the tunnel junction. A maximum sensitivity of $1.31\times 10^{8}$ ( $3.382\times 10^{6}$ ) is achieved for fully filled nanogap in CG TFET (HJ TFET) for dielectric constant 12.

Analysis of non-uniform hetero-gate-dielectric dual-material control gate TFET for suppressing ambipolar nature and improving radio-frequency performance**Project supported by the University Natural Science Research Key Project of Anhui Province, China (Grant No. KJ2017A502), the Introduced Talent Project of Anhui Science and Technology University, China (Grant No. DQYJ201603), the Excellent Talents Supporting Project of Colleges and Universities, China (Grant No. gxyq2018048), and

A tunnel field-effect transistor (TFET) is proposed by combining various advantages together, such as non-uniform gate–oxide layer, hetero-gate-dielectric (HGD), and dual-material control-gate (DMCG) technology. The effects of the length of non-uniform gate–oxide layer and dual-material control-gate on the on-state, off-state, and ambipolar currents are investigated. In addition, radio-frequency performance is studied in terms of gain bandwidth product, cut-off frequency, transit time, and transconductance frequency product. Moreover, the length of non-uniform gate–oxide layer and dual-material control-gate are optimized to improve the on-off current ratio and radio-frequency performances as well as the suppression of ambipolar current. All results demonstrate that the proposed device not only suppresses ambipolar current but also improves radio-frequency performance compared with the conventional DMCG TFET, which makes the proposed device a better application prospect in the advanced integrated circuits.

Electrical Characteristics Assessment on Heterojunction Tunnel FET (HTFET) by Optimizing Various High-κ Materials: HfO2/ZrO2

In this paper, DC performance of double gate tunnel field effect transistor with heterojunction has been assessed by various III-V compound semiconductor materials using 2-D Technology Computer Aided Design (TCAD) simulations. Different hetero high-κ dielectric materials like HfO2, ZrO2 have been incorporated to achieve better electrical characteristics, viz. high ON-state current drivability, improved switching ratio and high tunneling probability. In this work, lower band gap materials have been used as hetero gate dielectric to enhance mobility using band to band tunneling (BTBT), transconductance and steeper subthreshold-slope. The heterojunction TFET (HTFET) then incorporated with various hetero dielectrics (high-κ and low-κ combination), where the ZrO2 – SiO2 combination of dielectric having thickness of 2 nm both in front and back gate, attains maximum value of ION as 1.522 × 10-5 A/μm. The subthreshold swing (ss) has also been recorded best as 23.93 mV/dec in comparison with conventional homo dielectric i.e. SiO2-SiO2 oxide throughout the 50 nm channel of HTFET as 34.22 mV/dec, can serve as better alternative tunnel FETs in low power logic applications.

A novel vertical tunneling based Ge-source TFET with enhanced DC and RF characteristics for prospect low power applications

In this paper, we propose a novel germanium source based dual metal gate tunneling field effect transistor (VGeDMG). Design of device effectively suppresses lateral tunneling current component and facilitates dominance of vertical tunneling components which results in a substantially improved subthreshold slope. The dual gate in the design of the device gives the flexibility to control and improve the ON-current, OFF current and threshold voltage of the device significantly. In addition to the digital figure of merits, analog and RF performance of the proposed device is calculated and comparison with silicon source dual metal gate (conventional) TFET (SiDMG) and silicon source dual metal gate vertical TFET (VSiDMG) shows that the proposed device outperformed both the devices. The design fulfills the high-performance ON-state current of 1.20 mA, low standby power OFF-state current nearly of 3.63 fA, and SS 26 mV/decade indicating that the proposed TFET follows the ITRS roadmap for low standby power switch performance.

Analytical Modeling and Simulation-Based Optimization of Broken Gate TFET Structure for Low Power Applications

In this paper, we have reported a renovated silicon-based tunnel field-effect transistor (TFET) structure with a channel length of 21 nm. The proposed structure has been optimized and analytically modeled. The broken gate TFET (BG-TFET) shows very low ambipolar current, good subthreshold swing (SS) and ON-currents comparable to the contemporary structures of similar dimensions. The surface potential and the electric field inside the device are modeled by solving the 2-D Poisson’s equation. The drain current is also modeled based on Kane’s generation rate. The results obtained from the analysis are validated against Synopsys Sentaurus TCAD nonlocal tunneling model-based simulations.

Impact of band to band Tunneling on Transient performance of Dual Gate Tunnel Field Effect Transistor (TFET)

Tunnel Field Effect Transistor (TFET) is gated reverse biased P-I-N diode structured semiconductor device and can be considered as a reliable low power device. TCAD (Sentaurus 2D) simulations for various Gate metal work function (4.1-4.3 eV) shows that its ON-current (ION) arises from quantum mechanical band-to-band tunneling (B2BT) and observed that threshold Voltage (VT) for TFET decreases with increase in Gate metal work function. The thermionic emission of electrons in MOSFET limits the sub-threshold swing (SS) by 60 mV/dec whereas TFET has potential for low SS ie. SS<60 mV/dec. TCAD Simulations confirmed that that the Gate – Drain capacitance (Cgd) strongly follows the Gate capacitance (Cgg) all over the voltage range (0-0.9V) which increases the miller capacitance for TFET. It is investigated that for TFET, the injection of carriers into the channel is through B2BT which effectively couples the Gate charge to the Drain. A look up table based Verilog-A model is generated for TFET and used to simulate the static and dynamic behavior of TFET based digital circuit in Cadence spectre. Miller effect causes the peak voltage overshoots are noticed at the drain side during transient responses and can be responsible for dynamic power loss and high turn ON/OFF delay

Low leakage pocket junction-less DGTFET with biosensing cavity region

Low leakage current junction-less double gate tunnel field-effect transistor (JLDGTFET) with narrow band gap material pocket region of $Si_{0.7}Ge_{0.3}$ shows increased band to band tunneling and sharp subthreshold characteristics to meet low power, high speed digital and memory applications. The proposed JLDGTFET exploits the junction-less behavior that supports reasonable values of ON/OFF currents as well as improved subthreshold parameters. First, the performance optimization of the JLDGTFET is carried out with different gate contact and oxide region materials in terms of $I_{ON}/I_{OFF}$ current ratio, subthreshold slope, and drain induced barrier lowering. The ON/OFF performance of the pocket $Si_{0.7}Ge_{0.3}$ JLDGTFET with cavity region is also examined to enhance the sensing capability for biomolecules present in the atmosphere that affect the dielectric constant of air present in the cavity and hence overall performance changes. The 2D/3D Visual TCAD tool is used to simulate novel thin body pocket $Si_{0.7}Ge_{0.3}$ JLDGTFET.

Performance enhancement of triple material double gate TFET with heterojunction and heterodielectric

In this paper, we proposed a 2 dimensional model of tripple material double gate Tunnel Field Effect Transistor (TM-DG TFET) with hetero-junction formed by germanium and silicon materials in the source-channel junction and heterodielectric gate stack is used with Silicon Dioxide (SiO2) and Hafnium Dioxide (HfO2) as dielectric materials. The electrical characteristics like surface potential, electric field, drain current and transconductance are demonstrated for the device by using commercially available 2D numerical device simulator Silvaco TCAD ATLAS. The variation of the drain currnet or ON current with the varying channel length (L), doping concentration of drain and source (NA and ND), thickness of device (tsi) and effective oxide layer thickness (tox) of the device is evaluated and presented. It is demonstrated that the proposed TM-DG TFET structure has better performance than single material and double material TFET. The proposed model shows a lower ambipolar current and a better ION/IOFF ratio. Moreover, the influence of Germanium/Silicon hetero-junction has reduces the tunneling barrier width is exactly depicted. Hence the ON current (10−3A) of the proposed device is improved at the level of CMOS transistors.

Analytical drain current model of stacked oxide SiO2/HfO2 cylindrical gate tunnel FETs with oxide interface charge

In this paper, we have developed an analytical drain current model of stacked oxide SiO2/HfO2 cylindrical gate tunnel field-effect transistor (CG TFET) by considering the effect of interface trap charge at Si–SiO2 interface nearby the source–channel junction. To model the channel potential, Poisson’s equation has been solved by using the parabolic approximation method in a cylindrical coordinate system with appropriate boundary conditions. The potential model has then been utilized for developing some expressions for minimum tunneling length, lateral electric field, and the drain current of stacked oxide SiO2/HfO2 CG TFET. The impact of the source/drain depletion region has been considered for improving the accuracy of the proposed model. The commercially available ATLAS™ 3D-based TCAD simulation data have been used to validate the proposed model results.

A Comparative Study on Scaling Capabilities of Si and SiGe Nanoscale Double Gate Tunneling FETs

In the last few years, an accelerated trend towards the miniaturization of nanoscale circuits has been recorded. In this context, the Tunneling Field-Effect Transistors (TFETs) are gaining attention because of their good subthreshold characteristics, high scalability and low leakage current. However, they suffer from low values of the ON-state current and severe ambipolar transport mechanism. The aim of this work is to investigate the performance of SiGe nanoscale Double Gate TFET device including low doped drain region. The electrical performance of the considered device is investigated numerically using ATLAS 2D simulator, where both scaling and reliability aspects of the proposed design are reported. In this context, we address the impact of the channel length, traps density and drain doping parameters on the variation of some figures of merit of the device namely the swing factor and the ION/IOFF ratio. The obtained results indicate the superior immunity of the proposed design against traps induced degradation in comparison to the conventional TFET structure. Therefore, this work can offer more insights regarding the benefit of adopting channel materials and drain doping engineering techniques for future reliable low-power nanoscale electronic applications.

New subthreshold performance analysis of germanium based dual halo gate stacked triple material surrounding gate tunnel field effect transistor

Abstract An accurate two dimensional subthreshold modeling of Germanium based Dual Halo Gate stacked Triple Material Surrounding Gate (Ge-DH-GS-TM-SG) tunnel field effect transistor is proposed for the first time in this paper. The model is solved by Poisson's equation using parabolic approximation method. The developed model gives analytical expressions for surface potential, electric field, threshold voltage, drain current, trans conductance to drain current ratio, subthreshold current and subthreshold swing are used to evaluate the short channel effects. The subthreshold swing of the proposed Ge-DH-GS-TM-SG-TFET is compared with Silicon based Single Halo Triple Material Surrounding gate TFET(Si-SH-TM-SG-TFET)and Triple Material Surrounding Gate TFET(TM-SG TFET). It is noticable that the proposed device Ge-DH-GS-TM-SG-TFET structure provides. poor outflow current IOFF (10−15A/μm), and remarkable improvement in ON current. (10−5A/μm).Moreover, the ION/IOFF ratio is 108. The developed model results are validated through comparison with 3-D sentaurus TCAD simulator results.

Temperature sensitivity analysis of vertical tunneling based dual metal Gate TFET on analog/RF FOMs

In this paper, we present a rigorous numerical simulation study on temperature sensitivity for tunnel field effect transistor (TFET). The presented temperature sensitivity analysis is studied on different digital, analog and RF figure of merits for conventional TFETs. In addition, sensitivities of the conventional TFETs are compared with proposed vertical tunneling-based TFET (V-DMGTFET) and detailed discussion is presented for the same. In comparative study, we observed that proposed V-DMGTFET is less sensitive to temperature variations compared to the conventional TFETs. This indicates that proposed V-DMGVTFET is more reliable to use in low power application at high temperatures compared to the conventional TFET.

A comprehensive investigation of TFETs with semiconducting silicide source: impact of gate drain underlap and interface traps

In this paper, we have investigated the effect of gate underlap, while using semiconducting silicide material as a source region, on the ambipolar and high-frequency performance of Tunnel Field Effect Transistors (TFETs). We demonstrated how to suppress the ambipolar conduction and enhance the ON current without deteriorating the performance of high-frequency switching characteristics of the double gate TFET by using the combined two methods. The ON to OFF current ratio (ION/IOFF) and subthreshold swing (SS) as figures of merit for DC performance have been investigated. The main analog performance parameters like the transconductance (gm) and unit-gain cutoff frequency (fT) are analyzed. Moreover, circuit level digital performance parameters like the fall propagation delay (tphl) and overshoot voltage (Vp) are inspected when the proposed design is utilized in an inverter circuit. Impact of effective oxide thickness and traps arising from manufacturing process on DC, analog, and circuit level performance is also investigated. TCAD simulation results reveal a significant enhancement in DC, analog and digital performance parameters of the proposed heterojunction TFET over Si-TFET that makes the proposed design more advantageous in the field of analog and digital applications.

Effect of interface trap charges on the performance of asymmetric dielectric modulated dual short gate tunnel FET

In this paper, the influence of interface trap charges on the characteristics of asymmetric dielectric modulated dual short gate tunnel field effect transistor (ADMDG-TFET) has been analyzed. The effect of a donor (positive) and acceptor (negative) trap charges with various concentrations on the device d.c characteristics are studied. A comparative analysis has been performed between symmetric silicon dual gate tunnel field effect transistor (DG-TFET) and ADMDG-TFET (both Si and Si0.3Ge0.7) with matching dimensions in the presence/absence of interface trap charges. It is found that a shift in threshold voltage (Vth) and subthreshold swing (SS) degradation are observed due to the presence of interface traps in both devices. However, the ADMDG TFET is more immune to Vth shift and SS degradation by acceptor and donor interface traps compared to silicon DG TFET. Also, the ambipolar current in ADMDG TFET is more suppressed than the silicon DG TFET in the presence of trap charges.