Gate Tunnel Field Effect Transistor Research Articles

Tweaking the Performance of Dopingless Nano-TFET with Misaligned Sandwiched Dual-Gate Structure

While scaling down the devices it is important not to compromise with the performance. Scaling of tunnel devices shows better performance than Field Effect Transistors (FETs). Charge Plasma based Dopingless Double Gate Tunnel Field Effect Transistor (DLDGTFET) with its various misaligned configurations are designed, discussed and analyzed in the presented work. Silicon is preferred as a choice of material. For various misalignment configurations, initially, bottom gate is shifted towards the right, then it is shifted towards left and at last bottom and top, both gates are misplaced for analyzing the device parameters, analog parameters and linearity parameters. By misalignment, it is observed that either the bottom gate is misaligned towards the right or left or both gates are being misaligned, device performance degraded. The basic structure shows the higher drain current, better drive current among other structures such as 15 μA. whereas source underlapped (SU100) structure shows the better subthreshold slope such as 20 mV/decade. But SU100 has the least amount of drive current. In the subthreshold region, BM100 has the maximum value of transconductance gain factor i.e. 104 V−1. When the bottom gate is shifted towards right i.e. for drain overlapped structure it was observed that it shows better linearity parameters and can be considered for low noise and low voltage applications.

Germanium Source Metal Drain Tunnel FET with Dual Dielectric Underlap

In this paper, we propose, design and simulate a new double gate (DG) tunnel field effect transistor (TFET), using germanium (Ge) source, dual dielectric gate oxide, gate/drain underlap and a metal drain. The device is designed to address two important issues of a conventional TFET, that is, the poor ON current (ION) and the presence of ambipolar conduction. In the proposed device, the use of Ge material for the source region and a dual dielectric gate oxide enhances the ION significantly and employing metallic drain and a gate-drain underlap fully suppresses the ambipolarity conduction. This can be attributed to the formation of a Schottky barrier at channel/drain interface. Two-dimensional (2D) calibrated simulation studies have been performed using the commercial TCAD device simulator. The results have shown that the ION has improved by almost ~3 orders whereas ambipolar current is completely suppressed in the proposed device in comparison to the conventional DG-TFET. Further, it has been found that the proposed device has a subthreshold slope (SS) of 35 mV/dec, ION of ~2×10−4 A/ μm and the ION to IOFF ratio (ION/IOFF) of ~1013. The proposed device performance can be improved further by optimizing various device parameters, like underlap length etc. A flow chart mentioning the key fabrication steps has also been proposed to fabricate the proposed device.

Performance Analysis on Effect of Variation in Oxide Material of Double Gate Tunnel Field Effect Transistor

In this paper structure of Double Gate Tunnel Field Effect Transistor work to increase the efficiency of the device performance of Tunnel Field Effect Transistors making it one of the potential candidates for small scale devices. The essential point of this research work is to consider the performance analysis of the structure. This work is accomplished with the assistance of tool Cogenda TCAD version 1.9.2. The designing of the device, simulation and correlation of results have been gotten on this tool. The section gives the stream of Research Methodology and clarifies the footsteps for Design and Simulation of Double Gate Tunnel Field Effect Transistor.

Sensitivity Analysis on Dielectric Modulated Ge-Source DMDG TFET Based Label-Free Biosensor

This work compares the performance of dielectric modulated (DM) based Ge-source dual material double gate (DMDG) Tunnel Field Effect Transistor (TFET) and conventional (C)-DMDG-TFET as label free biosensor through Technology Computer Aided Design (TCAD) simulator. Here, cavity is introduced both at source and drain sides of the fixed HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> dielectric to increase the capture area of biosensors. Sensitivity (S <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</sub> ) is extracted for both neutral and charged (positive/negative) biomolecules considering cavity is fully filled with different dielectric materials (k). We have reported the sensitivity with the variation in height of nanogap cavity (h <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">bio</sub> ) for neutral biomolecules in the cavity. The sensitivity of Ge-source DMDG-TFET is found higher than C-DMDG-TFET due to more conduction at the tunnel junction. Also, the subthreshold swing (SS), transfer characteristics, and I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> ratio of these biosensors are reported for different k and h <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">bio</sub> considering neutral/charged biomolecules. The sensitivity of partially filled nanogaps with biomolecules like decreasing, increasing, concave, and convex step profiles are reported for both the biosensors. The dynamic range (DR) of both the biosensors are extracted in presence of positive and negative charged biomolecules. The response time of Ge-source DMDG-TFET is reported at different k. A comparative study of proposed biosensor with other reported work is discussed. Finally, the sensitivity is extracted for DMDG-TFET considering other source material like GaAs, InAs, Si-Ge hetero stacked (HS), GaAs-InAs HS.

Suppression of Ambipolar Current and Analysis of RF Performance in Double Gate Tunneling Field Effect Transistors for Low-Power Applications

The present research letter is dedicated to a detailed analysis of a double-gate tunnel field-effect transistor (DG-TFET). The DG-TFET provides improved on-current (I_ON) than a conventional TFET via band-to-band (B2B) tunneling. However, DG-TFET is disadvantageous for low-power applications because of increased off-current (I_OFF) due to the large ambipolar current (I_amb). In this research work, a Si/GaAs/GaAs heterostructure DG-TFET is considered as research base for investigation of device performance.

Drain current characterization of dielectric modulated split gate TFET for bio-sensing application

This paper presents an analytical surface potential and drain current model of split gate (SG) Tunnel Field Effect Transistor (TFET) for label free detection of biomolecules e.g. protein, biotine, DNA, etc., utilizing the concept of underlap and dielectric modulation approach. A portion of the device channel is left open in between the splitted gates with a thin layer of silicon dioxide as adhesive layer. This open cavity acts as the binding site for the biomolecules to be detected which alters the effective capacitance of the region and hence modulates the device characteristic trend. The device electrostatics are developed by solving two dimensional Poisson’s equation and Young’s parabolic approximation and consequent drain current is then formulated applying Kane’s model. To assess the sensing ability of the device, both neutral and charged biomolecules with different dielectric values are immobilized within the cavity and the impact of variation in dielectric constant, charge density and height of biomolecules on device characteristics is analyzed. In addition to this, drain current sensitivity of the device is also investigated by varying the permittivity, charge density (both positive and negative) and height of the bio-species. All the analytical results are evaluated with corresponding Sentaurus TCAD simulated data to corroborate the accuracy of the derived model.

Low-K Dielectric Pocket and Workfunction Engineering for DC and Analog/RF Performance Improvement in Dual Material Stack Gate Oxide Double Gate TFET

In this paper, we investigate the effect of low K dielectric pocket on DC and analog/RF performance in dual material stack gate oxide double gate tunnel field effect transistor. For this, we have considered an optimized dielectric pocket at the interface of the source-channel tunneling junction to reduce the barrier width. A stack gate oxide (SiO2 + HfO2) with workfunction engineering is applied to improve the capacitive coupling, decrease the ambipolar, leakage currents and increase the ON-current (ION). In addition, the entire gate has been divided into three segments, named as tunnelling gate (M1) with workfunction (ϕ1), Control gate (M2) with workfunction (ϕ2) and auxiliary gate (M3) with workfunction (ϕ3). All the possible combinations of these workfunctions were considered to maintain dual work functionality. Further, technology computer-aided design (TCAD) simulations for these possible combinations were carried out and compared with single material stack gate oxide dual gate source dielectric pocket TFET (ϕ1 = ϕ2 = ϕ3). Simulation results shows that the workfunction combination (ϕ1 = ϕ3 < ϕ2) outperforms the other three structures. Further, the performance of this device is compared with dual material control gate source dielectric pocket TFET (DMCG-SDP-TFET) with SiO2 gate oxide. The dielectric pocket at the tunneling junction and workfunction engineering on the stack gate oxide shows significant enhancement in ON state current (1.47× 10− 4A/μm), ION/IOFF (3.14× 1012), point subthreshold slope (15.7mV/decade), transconductance (1.02× 10− 3S), cut-off frequency (1.93× 1011Hz) and significant changes in other analog/RF performance parameters, making this device suitable for high frequency and low power applications.

A novel source material engineered double gate tunnel field effect transistor for radio frequency integrated circuit applications

Tunnel field effect transistors (TFETs) have proved their potential for many possible electronic circuit applications. However, with the variety of TFET structures being worked upon it has been an unresolved challenge to optimize them for the applications to which they are best suited. In this paper we present a detailed comparative analysis of the linearity distortion and the radiofrequency (RF) performance parameters of a proposed heterojunction Mg2Si source double gate TFET (HMSDG-TFET) and a conventional homojunction Si source DG-TFET (SSDG-TFET). A source material engineering scheme is utilized to implement a staggered type 2 heterojunction at the source–channel junction by replacing the source material with Mg2Si (a low band gap material) to enhance the ON current (2.5 × 10–4 A µm−1), reduce the threshold voltage (0.26 V) and achieve a steeper subthreshold swing (10.05 mV decade−1). For linearity and distortion analysis, the figure of merit (FOM)-like higher-order transconductances, second- and third-order voltage intercepts, third-order intercept point, third-order intermodulation distortion, zero crossover point, 1 dB compression point, second-order harmonic distortion, third order harmonic distortion and total harmonic distortion have been examined. To portray the possible application of devices under consideration for RF integrated circuit applications, both structures are investigated for RF FOMs such as power gains, cutoff frequency (fT), maximum oscillation frequency (F max) and admittance parameters. Investigations carried out using a Silvaco ATLAS device simulator tool revealed that with fT approximately three orders higher (0.49 THz) and F max approximately two orders higher (0.9 THz) than that of a SSDG-TFET, the HMSDG-TFET is an appropriate candidate for use in high-frequency, high-linearity, low-distortion and low-power analog/RF applications.

Impact of uniaxial strain on the electronic and transport properties of monolayer α-GeTe

Density functional theory calculations are performed to explore the electronic and transport properties of monolayer α-GeTe under uniaxial strain. It is found that monolayer α-GeTe has an indirect band gap of 1.75 eV and exhibits worthwhile anisotropy along with high electron mobility. The electron mobilities reach 1974 cm2 · V−1 · s−1 and 1442 cm2 · V−1 · s−1 along the zigzag and armchair directions, respectively. When uniaxial strain is applied, our results show an appreciable strain sensitivity of electron mobility. The electron mobility dramatically increases by an order of magnitude around a special strain due to the shifts of conduction band minimum. In addition, we also construct a double gate tunneling field effect transistor (TFET) with a channel of monolayer α-GeTe. The steeper sub-threshold swing and higher ON/OFF ratio are observed by applying tensile strain to the channel. As a result, it indicates that the appropriate strain can significantly improve the performance of α-GeTe TFETs.

Modeling and simulation of a dual-material asymmetric heterodielectric-gate TFET

Analytical modeling of a dual-material asymmetric heterodielectric-gate tunnel field-effect transistor (FET) is carried out based on the Poisson equation and parabolic approximation techniques. An asymmetric gate with two materials having different work functions is used to eliminate the influence of the OFF-current (leakage current) and short-channel effects in the device. The lengths of metal 1 and metal 2 are taken to be 10 nm and 10 nm, respectively, and the device performance is analyzed. Expressions for the surface potential, electric field, and drain current are obtained by using a two-dimensional (2D) mathematical model, whose results are compared with those obtained using the Silvaco technology computer-aided design (TCAD) simulator, revealing good agreement. The proposed dual-material asymmetric gate tunnel FET produces an improved ON-current of 10−5 A/µm and a decreased OFF current of 10−10 A/µm, with an ON/OFF ratio of 105.

Vertically Extended Drain Double Gate Si1−xGex Source Tunnel FET : Proposal &amp; Investigation For Optimized Device Performance

This paper reports an unique approach to suppress ambipolarity and enhance drive current in tunnel field effect transistor (TFET) by incorporating vertically extending drain in double gate Si1−xGex source TFET. This structure has dual source extending laterally on both sides of the channel with vertically extended drain over the T-shaped channel (VD-DG-Si1−xGexS-TFET). Our study is based on calibrated exhaustive 2-D TCAD simulations. It advocates that the device performance is not only retained but significantly enhanced even by deploying only double gate instead of quadruple gate with Si1−xGex sources. Further the drive current can be significantly increased by optimizing the mole fraction (x) in Si1−xGex source. Our study reveals that the average subthreshold slope (SSavg) is 23.98 m V/dec (point SS (SSpoint) is 12.7 m V/dec with sub-60 m V/dec point SS for 107 orders of current change), drive current (ION) is 2.73× 10− 4 A/um and 46% improvement in transconductance as compared to the earlier reported drain engineered quardruple gate TFET. Further the device sensitivity analysis with respect to gate oxide dielectric constant, gate metal work-function, temperature and germanium mole fraction variation is also analyzed here. Moreover, in terms of device analog behaviour, the cut off frequency (ft) is reported as 38.93 GHz and 140% increment in gain bandwidth product (GWB) as compared to its quardruple gate alternative. This study proves the potentials of considered device structure as a promising candidate for ultra low power analog/RF and digital logic applications.

Analytical model of a novel double gate metal-infused stacked gate-oxide tunnel field-effect transistor (TFET) for low power and high-speed performance

Abstract In this work, an innovative structure of a novel double gate tunnel field-effect transistor (TFET) is proposed with a channel length of 20 nm.The gate dielectric regions have been renovated by inserting metal strips and using stacked gate-oxide concept. The device exhibits suppressed ambipolar current, excellent subthreshold swing and good ION/IOFF ratio. The proposed structure proves to be a promising candidate for high speed applications as it shows lesser gate-capacitance than conventional stacked-oxide gate structure. The surface potential and electric field have been modelled considering the depletion regions, using 2-D Poisson's equation with appropriate boundary conditions, based on parabolic potential approximation. A semi-empirical method has been utilized to incorporate the effect of mobile charges on the device characteristics. A physics-based model for charge and terminal capacitances has been derived, following the potential model. The drain current model is able to accurately predict the ambipolar current as well as the effects of drain voltage in saturation region. Proper optimization of the device structure has been performed to derive the best desired electrical characteristics. SILVACO ATLAS simulation data have been used to validate the analytical results of the proposed structure, thereby corroborating the precision of the present analytical model. Finally, an inverter circuit has been designed in CADENCE circuit-simulation environment to justify the usage of our device in low power and high speed digital circuit applications.

Electrical performance of InAs/GaAs0.1Sb0.9 heterostructure junctionless TFET with dual-material gate and Gaussian-doped source

In this work, we demonstrate the design of a dual-material gate and Gaussian-doped source heterostructure junctionless tunnel field-effect transistor (DMG-GDS-HJLTFET). Unlike the conventional dual-material gate heterostructure junctionless tunnel field-effect transistor (DMG-HJLTFET), the proposed structure uses a Gaussian-doped source and adopts InAs/GaAs0.1Sb0.9 as a heterojunction at the source and channel interface, where a polarization electric field is induced by the lattice mismatch in the InAs and GaAs0.1Sb0.9 Zinc blende crystal. At the same time, the control gate electrode of the proposed structure is divided into two parts, namely tunnel gate (TG) and auxiliary gate (AG). In this structure, TG is located near the source side and has a lower work function, while AG is located near the drain side and has a higher work function, which not only improves ON-state current (Ion) but also decreases the OFF-state current. The performance of the proposed device is analyzed and compared with that of DMG-HJLTFET; simulation results show improvements in Ion, subthreshold swing, transconductance (gm), cut-off frequency (fT) and gain bandwidth (GBW). Compared with conventional DMG-HJLTFET, the maximum Ion and gm of the DMG-GDS-HJLTFET are 4.1 × 10−4 A μm−1 and 1.27 × 10−3 S μm−1 at 1.2 V gate-to-source voltage (Vgs); further, average subthreshold swing of DMG-GDS-HJLTFET is only 13.6 mV Dec−1 at low drain voltages. Also, DMG-GDS-HJLTFET could obtain a maximum fT of 193 GHz at Vgs = 0.8 V and a maximum GBW of 55.7 GHz at Vgs = 1.12 V, respectively.

Photosensor Based on Split Gate TMD TFET Using Photogating Effect for Visible Light Detection

This paper reports a highly-sensitive and low power photosensor based on split gate tunnel field effect transistor (TFET) structure for visible light detection in wavelength ranging from 450-750 nm. The TFET based sensing device utilizes the photogating effect in a portion of transition metal dichalcogenide (TMD) channel. The optically tunable workfunction contrast between the two gates of dual material gate (DMG) TFET achieves significant gains in the overall device characteristics. It demonstrates high photo-to-dark current ratio of the order of 10 8 and variation in responsivity in the range between 10 3 AmW -1 to 10 -5 AmW -1 for V gs = -0.9 V. This paper further discusses the photodetector performance based on the position of the photogate on the tunneling or auxiliary side, the gate splitting ratio between the photosensing region and the metal, and the n-TFET based device design. The device performance has been analyzed using the analytical model for the optically controlled workfunction. This hybrid device consisting of an ultrathin channel sensitized with absorbing semiconductors while exploiting the characteristics of TFET leads to a new generation of highly sensitive photodetectors.

Metal Drain Double-Gate Tunnel Field Effect Transistor with Underlap: Design and Simulation

In this paper, we propose and simulate a novel double gate tunnel field effect transistor (DG-TFET) employing a metallic drain and a gate-drain underlap. The use of a metallic drain and an underlap results in complete ambipolar suppression in the proposed TFET. A 2D calibrated simulation studies have revealed that ambipolar current suppression of ~ 5 orders, without affecting the on-state current of the device, when the gate voltage is varied between 1 V and -1 V, is achieved in the proposed device in comparison to the conventional DG-TFET. The complete ambipolar reduction is attributed to the reduced band-to-band-tunneling (BTBT) rate because of the Schottky barrier formation at the channel/drain interface. Further, the use of gate/drain underlap suppresses the ambipolarity completely in the proposed device in comparison to the conventional one. An ON current (ION) and OFF current (IOFF) ratio (ION/IOFF) of ~ 1012 with a subthreshold slope (SS) of 63 mV/decade is achieved in the proposed device. Further, the effect of change of various parameters on the performance of the proposed device has been thoroughly studied. It has been observed that the performance can be optimized further by using the optimum value of these parameters. A process flow for the fabrication of the proposed device has also been given.

Analytical Modeling of Ion Sensitive Broken Gate TFET for pH Sensing Applications

In this letter, structural modification of a conventional tunnel field effect transistor (TFET) device is presented to act as an effective pH sensor. The change in hydrogen ion concentration in the aqueous solution is to be detected by the present broken gate (BG) TFET based pH sensor with its semiconducting material being modified as the electrolytic region. The chemical reactions at the interface of the gate dielectric and the electrolyte generate a surface charge density, making the device sensitive to pH. An analytical model of the BG TFET is developed here to capture the impact of pH variations on surface potential and drain current characteristics of the device. The sensitivity of the device is then investigated by extracting the threshold voltage shift as the pH values of the injected solution are varied. The accuracy of the analytical results is further corroborated by ATLAS simulator extracted data.

Design and investigation of a dual source and U-shaped gate TFET with n buffer and SiGe pocket

In this paper, we propose and simulate a novel structure of a double source and U-shaped gate tunnel field effect transistor (DS-UTFET) with an n buffer layer and n+ SiGe pocket. In order to reduce the OFF-state current, there is an n buffer layer under the n+ SiGe pocket in a sandwich stack; moreover, we use a source region overlap in both the vertical and lateral directions to enhance the electric field; as a result, considerable ON-state current and a high Ion/Ioff ratio are realized in the proposed structure. In our simulation, the DS-UTFET shows better performance than the UTFET, and the simulation results indicate that the ON-state currents of the DS-UTFET with and without an n buffer layer increase up to 2.52 × 10−4 A/μm and 2.47 × 10−4 A/μm, respectively, and the average subthreshold swing of the DS-UTFET with and without an n buffer layer is 35.0 mV/dec and 52.7 mV/dec, respectively, which ensures that the DS-UTFET has a fine analog and logic feature for applications; moreover, the maximum gm of the DS-UTFET with and without an n buffer layer is 519 µS/μm and 493 µS/μm at 1.4 V drain-to-source voltage (Vds). In addition, the RF performance of devices depends on the cut-off frequency (fT) and gain bandwidth (GBW), and the DS-UTFET with and without an n buffer layer could achieve a maximum fT of 25.7 GHz and 22.5 GHz, respectively. Meanwhile, the DS-UTFET with and without an n buffer layer could achieve a maximum GBW of 3.56 GHz and 3.06 GHz, respectively.

Investigation of Modified 1T DRAM with Twin Gate Tunneling Field Effect Transistor for Improved Retention Characteristics

This paper proposes a one transistor dynamic random access memory (1T DRAM) with localized partial insulator (LPI) to increase data retention time. Proposed 1T DRAM cell is based on twin gate tunneling field effect transistor (TGTFET) and has improved retention characteristics with LPI. The LPI inhibit stored carrier movement with high energy barrier. Key process sequence is suggested and device optimizations with parameter variation are also investigated with device simulation. As the barrier length increases, retention characteristics can be improved but also it causes a decrease in the read 1 current. An increase in LPI length within the appropriate range is required in the proposed 1T DRAM.

Impact of Interface Trap Charges on Analog/RF and Linearity Performances of Dual-Material Gate-Oxide-Stack Double-Gate TFET

This paper investigates the impact of different interface trap charges (ITCs) on dual-material gate-oxide-stack double-gate TFET (DMGOSDG-TFET) by introducing localized charges (donor/acceptor) at the interface of semiconductor/insulator. For this, we have observed the effects of different ITCs on both conventional dual material control gate tunnel field effect transistor (DMCG-TFET) and dual-material gate-oxidestack double-gate TFET with identical dimensions in terms of DC, analog/RF and linearity performance parameters. Both the devices with positive (donor) and negative (acceptor) ITCs, have been simulated using technology computer-aided design (TCAD) tool. To understand the impact of different ITCs on the DC and analog/RF performances, the parameters such as electric field, transfer characteristics, transconductance, parasitic capacitance, fT, GBP and TFP for DMGOSDG-TFET have been analyzed and compared with that of DMCG-TFET. Further, to analyze the effect of different ITCs on the linearity performances, the parameters VIP2, VIP3, IIP3 and IMD3 have been investigated and compared with that of the conventional DMCG-TFET. Simulation results demonstrate that DMGOSDG-TFET is more immune towards different types of ITCs as compared to the conventional DMCG-TFET. Hence, DMGOSDG-TFET is more reliable over the conventional device for ultra low power applications.

TCAD simulation of a double L‐shaped gate tunnel field‐effect transistor with a covered source–channel

In this work, the authors propose and simulate a double L-shaped gate tunnel field-effect transistor (DLG-TFET) with the covered source-channel. The proposed structure improves the ON-state current by increasing the linear tunnelling area and has excellent subthreshold characteristics. The simulation focuses on the performance improvement of the device under different longitudinal gate length L g , interlayer silicon thickness T si , gate and source overlap length L ov , and covered source depth L s . For optimal parameters, the ON-state current of the proposed DLG-TFET increases up to 3.53 × 10 -5 A/μm, and the current switch ratio( I on / I off ) is 4.28 × 10 11 at room temperature, moreover, a minimum subthreshold swing (SSmin) and an average subthreshold swing (SSave) are as low as 32.2 and 52.9 mV/Dec, respectively. Meanwhile, this work uses mixed device-circuit simulations to predict the performance of the inverter circuit implemented with proposed DLG-TFET.