Low leakage pocket junction-less DGTFET with biosensing cavity region

Suman Lata Tripathi,Vimal Kumar Agrawal,Raju Patel

doi:10.3906/elk-1807-186

Abstract

Low leakage current junction-less double gate tunnel field-effect transistor (JLDGTFET) with narrow band gap material pocket region of $Si_{0.7}Ge_{0.3}$ shows increased band to band tunneling and sharp subthreshold characteristics to meet low power, high speed digital and memory applications. The proposed JLDGTFET exploits the junction-less behavior that supports reasonable values of ON/OFF currents as well as improved subthreshold parameters. First, the performance optimization of the JLDGTFET is carried out with different gate contact and oxide region materials in terms of $I_{ON}/I_{OFF}$ current ratio, subthreshold slope, and drain induced barrier lowering. The ON/OFF performance of the pocket $Si_{0.7}Ge_{0.3}$ JLDGTFET with cavity region is also examined to enhance the sensing capability for biomolecules present in the atmosphere that affect the dielectric constant of air present in the cavity and hence overall performance changes. The 2D/3D Visual TCAD tool is used to simulate novel thin body pocket $Si_{0.7}Ge_{0.3}$ JLDGTFET.

Highlights

Technology scaling needs minimization of power dissipation, which enhances the battery life of portable devices.Multigate MOSFET structures designed over SOI wafers show more control over the gate in the subthreshold region and have low power consumption due to less leakage in comparison to conventional MOSFETs [1, 2]
The simulation is performed for the JLDGTFET ( Lg = 15 nm) in linear and saturation regions of operation and the performance is compared with a similar junction-based DGTFET as well as the DGMOSFET
The proposed JLDGTFET has very low off-state current due to the barrier provided by the p-type pocket region resulting in ION /IOF F current ratio up to 10 9 ( Lg = 15 nm), which is higher in comparison to the TDJLT [19], varying between 10 2 and 10 7 with Lg varying between 10 and 20 nm

Summary

Introduction

Technology scaling needs minimization of power dissipation, which enhances the battery life of portable devices.Multigate MOSFET structures (double-gate, triple-gate, and gate-all-around MOSFETs) designed over SOI wafers show more control over the gate in the subthreshold region and have low power consumption due to less leakage in comparison to conventional MOSFETs [1, 2]. The proposed junction-less double gate TFET (JLDGTFET) with p-type Si0.7Ge0.3 pocket region implantation mainly suppresses OFF-state leakage ( < 10−12 A/ μ m) and provides an additional barrier for the charge carriers by reducing the ambipolar nature of the tunneling current.

Results

Conclusion