Analytical drain current model of stacked oxide SiO2/HfO2 cylindrical gate tunnel FETs with oxide interface charge

Abstract

In this paper, we have developed an analytical drain current model of stacked oxide SiO2/HfO2 cylindrical gate tunnel field-effect transistor (CG TFET) by considering the effect of interface trap charge at Si–SiO2 interface nearby the source–channel junction. To model the channel potential, Poisson’s equation has been solved by using the parabolic approximation method in a cylindrical coordinate system with appropriate boundary conditions. The potential model has then been utilized for developing some expressions for minimum tunneling length, lateral electric field, and the drain current of stacked oxide SiO2/HfO2 CG TFET. The impact of the source/drain depletion region has been considered for improving the accuracy of the proposed model. The commercially available ATLAS™ 3D-based TCAD simulation data have been used to validate the proposed model results.