Gate Oxide Process Research Articles

Gate oxide process control optimization by x-ray photoelectron spectroscopy in a semiconductor fabrication line

X-ray photoelectron spectroscopy is a metrology technique that is used for in-line control of decoupled plasma nitridation processes in the fabrication of logic devices. This article shows XPS results of thickness and composition obtained on two types of gate oxide nitrided by a decoupled plasma nitridation process. Measurements are performed in specific test structures with an x-ray spot which can be focused down to 35μm, enabling process control directly on products. First, XPS is used to characterize and quantify the chemical composition of a SiON layer. The Results show that the nitrogen composition in a SiON layer decreases at a fast rate during the initial days after nitridation processing and stabilizes with time. Second, measurements are performed on products with the objective of transferring process control from monitor to product wafers. In this regard, comparison of nitrogen dose and thickness uniformity on monitor and pattern wafers show similar trends, indicating that measurements of nitrogen dose and thickness on monitor and product wafers give the same information. Third, different mapping protocols are studied on products to identify the best compromise between throughput and an optimized mapping representative of the process distribution. An optimized process control strategy of gate oxides with results is discussed in this article.

Optimization of GaN MOS capacitors and FETs

AbstractIn this paper, three different gate oxide processes were explored and compared. All MOS capacitors were fabricated on n‐type GaN epitaxial layers grown by MOCVD on sapphire substrates. C‐V measurements were performed on the three samples and their characteristics were compared. The very small interface‐state density makes OX3 a very good process choice for GaN MOSFETs and the trend of decreasing interface‐state density deeper into the bandgap allows the demonstration of GaN inversion‐mode MOSFET.Both accumulation and inversion‐mode MOSFETs were fabricated and characterized using OX3 process conditions. Field‐effect mobilities were extracted on both circular and linear devices with different channel lengths. Mobilities in two perpendicular directions in (0001)‐plane show similar values. Current collapse testing was also performed on our GaN MOSFETs and no current collapse was observed. In addition, an NMOS inverter stage, utilizing an enhancement‐mode MOSFET and a depletion‐mode MOSFET has also been demonstrated and characterized. (© 2008 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

Defect Generation in p-MOSFETs Under Negative-Bias Stress: An Experimental Perspective

In this paper, a focused review is made of our previously reported (2002-2007) work on negative-bias temperature-instability (NBTI) measurement and analysis. Using suitable cross-reference to other published work, the impacts of stress condition, characterization technique, and gate-oxide process on measured NBTI parameters are reviewed. The large scatter of measured time, bias, and temperature dependencies of NBTI, which are observed in published literature, is carefully analyzed. A common framework for NBTI physical mechanism is suggested and discussed. Issues lacking proper understanding at present are also highlighted.

Influence of starting material on analog technology fabrication yield and device component performance

Choice of substrate used for analog complementary metal-oxide-semiconductor (CMOS) technologies impacts device performance and fabrication yields significantly. This study examines the impact of low-angle (<5°) off-axis Si(100) substrate rotated around ⟨110⟩ axis and 0° Si(100) on-axis starting material on inline process control, parametric device performance, and ultimately fabrication yields. The interaction of thermal processes and silicon epitaxial growth process variation on inline photoalignment and its influence on device design and performance is discussed for both types of substrates. The device components include 3 and 5V analog CMOS, lateral p-n-p bipolar transistor, junction field effect transistors, and drain extended transistors, DENMOS and DEPMOS, where the drain extensions are formed using well implants. The necessity to reintegrate silicon epitaxial growth, well photolithography and implants, Vt implants, and gate oxide process loop to accommodate substrate crystal orientation changes will be presented. A novel front-end-of-the-line integration scheme to improve interwafer and intrawafer electrical distributions with excellent transistor matching and 1∕f noise performance for aforementioned device components will also be discussed in this context.

Fabrication of 4H-SiC p-Channel MOSFET with High Channel Mobility

We have fabricated inversion-type p-channel MOSFETs on 4H-SiC substrates. In this paper, influences of gate oxidation process on the properties of p-channel MOSFETs were investigated. The gate oxide was formed under these three conditions: (i) dry oxidation, (ii) dry oxidation following wet re-oxidation, and (iii) wet oxidation. The C-V measurements of p-type 4H-SiC MOS capacitors revealed that wet oxidation process reduced the interface states near the valence band. The p-channel MOSFET with low interface states near the valence band indicated low threshold voltage (Vth), high field effect channel mobility (μFE) and low subthreshold swing (S). We obtained 4H-SiC p-channel MOSFET with high μFE of 15.6cm2/Vs by using wet oxidation as gate oxidation process.

Effect of the oxidation process on the electrical characteristics of 4H–SiC p-channel metal-oxide-semiconductor field-effect transistors

We fabricated inversion-type 4H–SiC p-channel metal-oxide-semiconductor field-effect transistors (MOSFETs). The electrical properties of the p-channel MOSFETs depended on the gate oxidation process. We found that wet oxidation process was effective for improving the channel mobility of the p-channel MOSFET, and obtained the field-effect channel mobility μFE of 15.6cm2∕Vs by using that process. Measurements of the p-type MOS capacitors implied that the SiO2∕SiC interface states around the valence band affected the channel mobility and threshold voltage of the p-channel MOSFETs. We also investigated temperature dependences.

Overview on electrostatic discharge protection designs for mixed-voltage I/O interfaces: design concept and circuit implementations

Electrostatic discharge (ESD) protection design for mixed-voltage I/O interfaces has been one of the key challenges of system-on-a-chip (SOC) implementation in nano-scale CMOS processes. The on-chip ESD protection circuit for mixed-voltage I/O interfaces should meet the gate-oxide reliability constraints and prevent the undesired leakage current paths. This paper presents an overview on the design concept and circuit implementations of the ESD protection designs for mixed-voltage I/O interfaces without using the additional thick gate-oxide process. The ESD design constraints in mixed-voltage I/O interfaces, the classification and analysis of ESD protection designs for mixed-voltage I/O interfaces, and the designs of high-voltage-tolerant power-rail ESD clamp circuit are presented and discussed.

The electrical and physical analysis of Pt gate/Al2O3/p-Si (100) with dual high-k gate oxide thickness for deep submicron complementary metal-oxide-semiconductor device with low power and high reliability

In order to examine the electrical and physical properties of Al2O3 layers with dual thickness on a chip, Pt gate/Al2O3 with dual thickness/p-type Si (100) samples were fabricated using atomic-layer deposition, separation photolithography, and 100:1 HF wet etching to remove the first Al2O3 layer. Dual metal-oxide-semiconductor (MOS) capacitors with thin (physical thickness, ∼4.5 nm, equivalent oxide thicknesses (EOT): 2.8 nm) and thick (physical thickness, ∼8.2 nm, EOT: 4.3 nm) Al2O3 layers showed a good leakage current density of −5.4×10−6 A/cm2 and −2.5×10−9 A/cm2 at −1 V, respectively; good reliability characteristics as a result of the good surface roughness; low capacitance versus voltage measurements (C-V) hysteresis; and a good interface state density (∼7×1010 cm−2eV−1 near the midgap) as a result of pre-rapid thermal annealing (pre-RTA) after depositing the Al2O3 layer compared with the single MOS capacitors without the pre-RTA. These results suggest that dual Al2O3 layers using the dual gate oxide (DGOX) process can be used for the simultaneous integration of the low power transistors with a thin Al2O3 layer and high reliability regions with a thick Al2O3 layer.

Organic Contamination Control in Silicon Surface Processing

Introduction As semiconductor devices continue to be highly integrated and their geometry also continues to shrink, not only metallic and particulate contamination but also trace chemical contamination, particularly organics, adsorbed on the surface of silicon wafers has an increasingly detrimental impact on the performance and yield of semiconductor devices [1-4]. The adsorption of airborne organic volatiles onto the surface of silicon wafers leads to unintentional hydrophobization (or wettability changes) and haze generation. Time dependent haze on silicon surfaces is generated by the interaction of organic volatiles on the silicon surfaces with moisture [5]. The haze on silicon surfaces is widely known to prevent the effective removal of metallic contaminants from the silicon surface, as well as to prevent the uniform etching of silicon surfaces and insulator films during aqueous chemical treatment [6]. Airborne organic volatiles also cause degradation haze on the lenses and mirrors of wafer steppers/scanners in photolithography [7], where high energy photons in a short wavelength of light stand a better chance of breaking the bonds of several organic species commonly present in cleanrooms, ultimately transforming them into reactive species that stick to optical surfaces. The resultant haze on the optical surfaces causes a transmission loss of light, resulting in a reduction in image uniformity. Trace organic volatiles on silicon surfaces can also cause an accelerated oxidation rate due to the presence of moisture generated by the decomposition of organic compounds during the rapid thermal oxidation of silicon wafers due to the incomplete combustion of organic volatiles before the start of rapid thermal oxidation. Furthermore, trace organic volatiles have an increasingly detrimental impact on the performance, yield, and reliability of ever smaller semiconductor devices. It has been shown that such organic contaminants have deleterious effects on the gate oxide integrity (GOI) in MOS transistors during wafer transport/storage before the oxidation process [1, 2], as well as after the gate oxidation process prior to polycrystalline silicon deposition [8]. Figure 1 shows the degradation of the time-dependent dielectric breakdown (TDDB) characteristics of gate oxide films for MOS capacitors contaminated by organic volatiles. As alternative gate insulating film, such as HfO2 and Al2O3 are introduced for low-power CMOS applications, organic contaminants residing at the interface between gate electrode and gate insulation films can degrade the gate dielectrics. In addition, trace organic volatiles on silicon surfaces cause a lot-to-lot deviation of the film thickness due to variable incubation times in chemical vapor deposition (CVD), as shown in Fig. 2 [9]. They can also cause the locally abnormal growth of CVD films. Especially in low temperature deposition, such as the selective epitaxial growth of Si or SiGe in the source drain region, organic contaminants or residual carbon contaminants can generate defects in the deposited film [10].

A CAD assisted design and optimisation methodology for over-voltage ESD protection circuits

To reduce the cycle time and the cost of the design of ESD tolerant over-voltage I/O cells, a methodology for pre-silicon ESD protection optimisation is described, based on Technology Computer Aided Design (TCAD) (device level) and compact (circuit level) simulation studies. Using this methodology, first time right ESD tolerant over-voltage I/O cells were designed in a silicided 0.25 μm CMOS dual gate-oxide process. The methodology consists in a precise TCAD process calibration, a cascoded snapback NMOS compact model definition valid under ESD conditions, a model parameter extraction based on TCAD data and, finally, circuit level optimisation of the I/O protection circuits. Very good agreement was achieved between the simulated pre-silicon characteristics and the experimental behaviour of the I/O protection circuits.

Gate oxide metrology and silicon piezooptics

We describe the use of spectroscopic ellipsometry and other characterization techniques for gate oxide process metrology in manufacturing of CMOS transistors for the 130 nm node and beyond. Specifically, we describe the difficulties associated with the introduction of silicon-on-insulator (SOI) substrates, alternative gate dielectrics (silicon oxynitride or metal oxides), and strained Si channels. We predict that spectroscopic ellipsometry by itself will no longer be sufficient for gate oxide metrology, which will make the CMOS gate stack process much more difficult to control.

저온 래디컬 산화법에 의한 고품질 초박막 게이트 산화막의 성장과 이를 이용한 고성능 실리콘-게르마늄 이종구조 CMOS의 제작

We have developed a low-temperature, and low-pressure radical induced oxidation (RIO) technology, so that high-quality ultrathin silicon dioxide layers have been effectively produced with a high reproducibility, and successfully employed to realize high performace SiGe heterostructure complementary MOSFETs (HCMOS) lot the first time. The obtained oxide layer showed comparable leakage and breakdown properties to conventional furnace gate oxides, and no hysteresis was observed during high-frequency capacitance-voltage characterization. Strained SiGe HCMOS transistors with a 2.5 nm-thick gate oxide layer grown by this method exhibited excellent device properties. These suggest that the present technique is particularly suitable for HCMOS devices requiring a fast and high-precision gate oxidation process with a low thermal budget.

Physical and Electrical Examination of CMOS Transistors with Dual Gate Oxide Process Formed by Ion Implantation

The physical and electrical effects of two ion implantation approaches for dual gate oxide (DGO) formation have been examined in a sub-2 nm gate oxide, high performance complementary metal oxide semiconductor (CMOS) logic process. A masked fluorine implant prior to gate oxidation was used to control the silicon substrate oxidation rate. This process results in a simple method to precisely increase gate oxide thickness and decrease gate current in specific gate current sensitive subcircuits. The fluorine DGO methodology also produced well-behaved transistor characteristics for both thin and thicker gate oxide transistors. Using argon to produce DGO resulted in severely degraded gate oxide and transistor characteristics. Significantly higher gate current for a given oxide thickness resulted with argon implant. In addition, the argon implant produced interface states that badly degraded transistor characteristics. Transmission electron microscopy showed defect regions for the case of DGO with argon implant that was not observed with the fluorine implant. In addition, Raman scattering showed residual amorphous silicon regions with argon implantation that were not observed for the case of DGO by fluorine implantation. © 2002 The Electrochemical Society. All rights reserved.

Polyreoxidation process step for suppressing edge direct tunneling through ultrathin gate oxides in NMOSFETs

In this work, we identify polyreoxidation as a process step for selectively thickening the gate oxide at the edges (in the gate overlap region), and hence for suppressing the edge component of direct tunneling through ultrathin gate oxides in NMOSFETs. It is shown that by varying the different polyreoxidation parameters viz: temperature and polyreoxidation time it is possible to achieve different levels of gate oxide edge thickening. This essentially implies that a desired level of gate leakage current may be maintained without modifying the gate oxidation process significantly.

Process Design for Preventing the Gate Oxide Thinning in the Integration of Dual Gate Oxide Transistor

In this study, a method is proposed to alleviate a gate oxide (GOX) thinning problem at the edge of shallow trench isolation (STI), when STI is adopted in the dual gate oxide process (DGOX). It is well known that the DGOX process is usually used for realizing both low and high voltage operating parts in one chip. However, it is found that severe GOX thinning occurs from 320 Å (in active area) to 79 Å (at STI top edge) and a dent profile exists at the top edge of STI, when conventional DGOX and STI processes are adopted. In order to solve these problems, a new DGOX process is used in this study. The GOX thinning is prevented mainly by a combination of a thick sidewall oxide with SiN pullback. Therefore, good subthreshold characteristics without a so-called double hump are obtained by the prevention of GOX thinning and a deep dent profile.

Determination of the Fowler–Nordheim tunneling parameters from the Fowler–Nordheim plot

A wide range of values have been reported for the Fowler–Nordheim (F–N) parameters A and B for the tunneling emission in MOS capacitor structures. The parameters A and B are respectively the pre-exponential factor and the exponent in the F–N equation. In this study, it is shown that the oxide thickness is the most influential factor in determining the accuracy of the parameter B. The uncertainty of the oxide thickness may be responsible for the discrepancies in the reported values for B. The discrepancy in the value of A was attributed to the difference in the measurement conditions and gate oxide processing.

Channel engineering using RTA prior to the gate oxidation for high density DRAM with single gate CMOS technology

A non-uniform lateral boron profile along the channel width is observed in a buried-channel p-MOSFET and a memory cell transistor when BF 2 implantation is applied at the dose of ∼10 13 cm −2 to form a channel. SIMS profile analysis and two-dimensional simulation results show that this abnormal profile is formed by transient enhanced diffusion (TED) due to BF 2 implantation damage during gate oxidation process. It is found that RTA process just prior to the gate oxidation is useful to eliminate the TED of boron so that inverse narrow width effect, short channel effect and threshold voltage fluctuation are remarkably improved in a buried-channel p-MOSFET. In addition, the RTA process can also reduce BF 2 implantation dose without decreasing threshold voltage by the suppression of boron diffusion in a cell transistor. Therefore, the retention time of DRAM can be enhanced by reducing space charge region field in a cell transistor due to lower boron concentration compared with a conventional device.

Synthesis of a new manufacturable high-quality graded gate oxide for sub-0.2 μm technologies

Graded gate oxide process involves a two-step synthesis of growing an oxide at a temperature above the viscoelastic temperature (T/sub VE/) onto a pregrown low temperature thermally grown SiO/sub 2/ layer to form a composite graded SiO/sub 2/ structure. The cooling rate is carefully modulated near T/sub VE//spl sim/925/spl deg/C to enhance growth induced stress relaxation. The pregrown SiO/sub 2/ layer provides grading and is a sink for stress accommodation for the final high temperature SiO/sub 2/ forming the interface. Both grading and modulated cooling generate a strain-free and planar Si/SiO/sub 2/ interface. Such an interface delivers significant enhancement in all aspects of device reliability and performance. These oxides are of very high-quality, robust, and manufacturable with a process capability index, C/sub pk/>1.5. Graded gate oxide is already in the primary path of our 0.16 /spl mu/m and 0.12 /spl mu/m technologies.

Sensitivity of SHG-measurements on oxide deposition process parameters

We present a comparison of SHG-measurements at the Si/SiO2-interface with electrical characterization to demonstrate the ability of non-linear optical methods for the analysis of interfaces. The Si/SiO2-interfaces under investigation are deposited oxides on Si(001) substrate which were treated in a rapid thermal processing (RTP) chamber. The variation of oxide process parameters, namely the temperature of the post deposition annealing (PDA)-temperature and cooling rates result in a variation of the amplitude of the non-linear optical radiation from the Si/SiO2-interface. Standard electrical characterization of identical samples reveal correlated changes in the defect concentration at and near the interface. These results show that the method of SHG may provide a fast and non-destructive characterization- and process-control-tool for in situ parameter analysis during gate-oxide processing.

Effect of N+ Ion Implantation and Gox Process on in and B Channel Profile

AbstractIn this work, we report on the effect of different dual gate oxide (DGox) processes on the electrical properties of CMOS devices in deep submicron embedded DRAM (eDRAM) technology. Also discussed, is the effect of N+ Ion Implantation on the diffusion / segregation behaviour of B and In channel dopants. In particular, it will be shown that the N+ dose required to obtain a certain combination of dual gate oxide thickness varies with the gate oxide process. Effects of N+ dose on the In and B channel profiles are studied using SIMS. The impact of “thickness-equivalent” DGox processes on short channel effect (SCE) and carrier mobility is analyzed and tradeoffs for optimization of device performances are discussed.