Process Design for Preventing the Gate Oxide Thinning in the Integration of Dual Gate Oxide Transistor

Abstract

In this study, a method is proposed to alleviate a gate oxide (GOX) thinning problem at the edge of shallow trench isolation (STI), when STI is adopted in the dual gate oxide process (DGOX). It is well known that the DGOX process is usually used for realizing both low and high voltage operating parts in one chip. However, it is found that severe GOX thinning occurs from 320 Å (in active area) to 79 Å (at STI top edge) and a dent profile exists at the top edge of STI, when conventional DGOX and STI processes are adopted. In order to solve these problems, a new DGOX process is used in this study. The GOX thinning is prevented mainly by a combination of a thick sidewall oxide with SiN pullback. Therefore, good subthreshold characteristics without a so-called double hump are obtained by the prevention of GOX thinning and a deep dent profile.