Novel Dual Gate Oxide Process with Improved Gate Oxide Integrity Reliability

Abstract

We have investigated the degradation of thick gate oxide in conventional dual gate oxide process; thick oxide grown by a new du al gate oxide process showed an improved gate oxide integrity and reliability compared with that of a conventional dual gate oxide process. To meet the requirement of integrating 3 and 6 nm dual gate oxide on a single chip operated under the bias of 1.8 and 2.5 V, respectively, this novel dual gate oxide process flow, without gate oxide thinning at a shallow trench isolation corner, was dev el- As complementary metal oxide semiconductor (CMOS) logic scales down, it needs ultrathin gate oxides and a reduced operating voltage for high performance. At the same time, however, an increas- ing number of applications require dual voltage or dual gate oxide (DGO) on a chip to interface to a higher external voltage. Moreover, to facilitate merged logic and memory circuits, DGO for memory and logic is also required. In a conventional DGO process using wet etching, a thick oxide layer is formed by reoxidizing the residual oxide after partially etching the pregrown oxide, while a thin oxide layer is grown on a clean silicon surface after thoroughly etching the pregrown oxide. Thus, the thick oxide layer in the DGO process has a tendency to poor reliability compared with a thin oxide layer and single-step-grown oxide with the same thickness. 1-4 In this paper, we describe a newly developed modified DGO (MDGO) process with higher reliability in thick oxide. By intensive study of the degradation of thick oxide through electrical and geo- metrical analyses, we report that the thick oxide is degraded due to the combined effect of severe thinning and grooving at a shallow trench isolation (STI) corner and the roughened surface of the resid- ual oxide before the second oxidation.