Gate Oxide Process Research Articles

The effect of silicon gate microstructure and gate oxide process on threshold voltage instabilities in p/sup +/-gate p-channel MOSFETs with fluorine incorporation

Several phenomena have been identified which significantly reduce boron penetration for boron difluoride-implanted or boron/fluorine-co-implanted gates The fluorine-induced threshold-voltage (V/sub TP/) shift is minimized by using an as-deposited amorphous silicon gate and a gate oxide process that excludes hydrogen chloride. The V/sub TP/ shift can be reduced to a level close to that of a boron-implanted gate, while maintaining the fluorine incorporation at the SiO/sub 2//Si interface to lower interface-state density. A model based on the fluorine atom distribution is proposed to explain the observed V/sub TP/ shift. >

Contamination due to process gases

Abstract A survey is given of the BOC Group technical research programs, whose purpose is to relate purity in gas processing to ULSI device parameters. Results from the following research programs are presented: how inert gas purity affects the Ti silicide for IGFET metallization; the effects of argon versus nitrogen used in silicon gate oxidation process steps; and preliminary work on a new gas analytical tool, Atmospheric Pressure Ionization Mass Spectrometry (APIMS), which allows measurement of sub ppb impurity levels in processing gases.

ESD phenomena in graded junction devices: C. Duvvury, R. N. Rountree, H. J. Stiegler, T. Polygreen and D. Corum. 27th a. Proc. IEEE/IRPS Int. Reliab. Phys. Symp., 71 (1989)

A non-uniform lateral boron profile along the channel width is observed in a buried-channel p-MOSFET and a memory cell transistor when BF2 implantation is applied at the dose of ∼1013 cm−2 to form a channel. SIMS profile analysis and two-dimensional simulation results show that this abnormal profile is formed by transient enhanced diffusion (TED) due to BF2 implantation damage during gate oxidation process. It is found that RTA process just prior to the gate oxidation is useful to eliminate the TED of boron so that inverse narrow width effect, short channel effect and threshold voltage fluctuation are remarkably improved in a buried-channel p-MOSFET. In addition, the RTA process can also reduce BF2 implantation dose without decreasing threshold voltage by the suppression of boron diffusion in a cell transistor. Therefore, the retention time of DRAM can be enhanced by reducing space charge region field in a cell transistor due to lower boron concentration compared with a conventional device.

Interface properties of two step thin gate oxides using 1,1,1-trichloroethane

The two step gate oxidation process is studied for growing highly reliable gate oxides for MOS devices using 1,1,1-trichloroethane as a chlorine source. In this process a part of the oxide layer is grown initially at a low temperature which is known to give a low density of defects in these oxides. This is followed by a high temperature growth process to get the desired oxide thickness as well as passivating these oxides against mobile ions. However, the effect of this two step process on the interface parameters has not been reported so far. In this study, the interface state density of the two step process is determined vis-a-vis the one step oxidation process. It is found from quasi-static C-V measurements that the interface state density of the two step process is about 15% lower than that of the conventional one step process near the valence band edge but has the same value near mid gap.

High-quality deposited gate oxide MOSFET's and the importance of surface preparation

The fabrication and electrical characteristics of MOSFETs incorporating thin gate oxides deposited by a modified plasma-enhanced chemical-vapor-deposition (PECVD) process are reported. The gate oxide deposition and all subsequent steps were carried out at or below 400 degrees C. These results represent the first demonstration of near-thermal-gate oxide quality. MOSFETs fabricated using a low-temperature PECVD gate oxide process without requiring a high-temperature anneal. The ultimate performance of the deposited oxide devices is shown to be critically dependent on the degree of process induced microroughness of the starting silicon surface. Low-temperature effective mobility measurements are used to compare inversion-layer scattering mechanisms in these devices. >

Preoxidation UV Treatment of Silicon Wafers

As the thickness of gate oxides employed in high density MOS integrated circuits decreases, more attention must be given to the condition of the silicon surface prior to the thermal gate oxidation process. Among others, organic contaminants are of particular concern in this case. In this paper a treatment, which is aimed at the removal of organics, is studied as a step prior to thermal growth of very thin (<20 nm) gate oxides. The results obtained show that such a treatment causes: (i) growth of up to 1.5 nm thick oxide which stabilizes the silicon surface before oxidation, (ii) reduction of carbon content in the subsequently grown thermal oxide, and (iii) improved dielectric strength in gate oxides provided that water vapor is added to oxygen during the exposure of silicon to the UV treatment. On the other hand, no impact of the preoxidation UV treatment was found on interface trap density and oxide fixed charge in the subsequently formed structure. Considering these findings, the preoxidation treatment is recommended as an effective and easy to implement addition to the standard wafer cleaning process.

Total-Dose and Charge-Trapping Effects in Gate Oxides for CMOS LSI Devices

The effect of gamma irradiation on CMOS devices fabricated using 3 Micron CMOS BULK process has been studied as a function of gate oxide processing and subsequent annealing. Threshold shifts, speed degradation, and power supply currents were measured as a function of total dose up to 106 Rad (Si). Using hot electron injection techniques, trapping densities and capture cross-sections of the traps in each oxide type have been determined at pre- and post-irradiation levels. Power supply leakage and speed performance of the devices were recovered within three to five hours by annealing them at 125°C, +10 V bias.

Numerical estimation of the doping profile and threshold voltage of the boron isolation region in MOS devices

The doping profile and threshold voltage of the channel stop used in delineating an MOS device structure is dependent upon all the high temperature processing steps used in the complete fabrication process. In this paper a numerical mothod is used to evaluate the effectiveness of a boron-doped channel stop, and conclusions are drawn as to the order in which the diffusions, used to form the transistor and its isolation region, should be performed for the optimum device performance. Using the numerical method, the final threshold voltage for a wide range of initial doping conditions (both by diffusion and implantation) are presented in graphical form for two commonly used gate-oxidation processes. The effect of repeated gate oxidations on the channel stop is also considered.

Investigation of Radiation Effects and Hardening Procedures for CMOS/SOS

Ionizing radiation effects and hardening procedures have been investigated using simple CMOS/SOS circuits fabricated with SiO2 gate insulators. A modified gate oxidation process using steam and HCl has resulted in improved gate oxide hardness -- with threshold voltage shifts of less than two volts up to a total dose of 106 rads(Si). Radiation-induced n-channel leakage currents were reduced by more than two orders of magnitude by using a deep boron ion implant and appropriate process ing techniques. Post-irradiation values of less than 0.5?A/mil have been obtained using this procedure. Studies of charge buildup at the silicon-sapphire interface indicate an effective positive charge in the range of 1011 cm-2 to 1012 cm-2 - peaking at a total dose of about 105 rads (Si). This effective charge decreases for increasing doses above 5×105 rads(Si). The decrease is attributed to radiation-induced interface states.

Redistribution of boron and phosphorous in silicon after two oxidation steps used in MOST fabrication

Redistribution of boron and phosphorous impurities in silicon resulting from two consecutive oxidation steps is calculated by using either the method of Green's function or by separating the redistribution after the first oxidation into a constant and error function term. An approximate but analytical solution for redistribution after the second oxidation is then obtainable. Employing a variety of oxidation parameters normally used in several MOS-transistor fabrication processes, the impurity profiles at the end of the second (gate) oxidation process is calculated for each case for both boron- and phosphorous-doped substrates. These profiles compare well with those obtained experimentally from <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C-V</tex> measurements made on Schottky-barrier diodes deposited on silicon wafers that underwent the same oxidation processes.

Process Techniques and Radiation Effects in Metal-Insulator Semiconductor Structures

In the search for a means to minimize the radiation sensitivity of MOS transistors, a study was made on the interrelation between sensitivity to space radiation in MOS devices and the method of fabricating the gate oxide film of these devices. Both MOS capacitors and transistors were studied, using automatic plotting of capacitance-voltage and channel current gate voltage characteristics. For both types of device, the oxides studied were fabricated under varied but closely controlled conditions. Both special laboratory furnaces and production type of furnaces were used to grow the gate oxide. As a result of these experiments, the following conclusions were reached. (1) Gate oxide process techniques vary in their effect on the sensitivity of MOS structures to high-energy radiation by an order of magnitude. (2) The reproducibility of the degree of sensitivity to radiation is greater when steam-growth of oxides is used, rather than dry-oxygen growth. (3) In general, the nearer the prebombardment C-V characteristic of an MIS insulator is to the ideal (charge-free) charateristic, the less sensitive is the MIS device to radiation. (4) A key experiment was the successful hardening, by a factor of 2 to 3 in the voltage shift, of dry oxide layers by the addition of a coating of phosphorus containing glass. (5) Several other process parameters (e. g. crystallographic orientation of the silicon) can be ruled out as to their influence on radiation sensitivity. (6) The present levels of radiation sensitivity in mass-produced devices can be reduced by changes in process technique.