Physical and Electrical Examination of CMOS Transistors with Dual Gate Oxide Process Formed by Ion Implantation

Abstract

The physical and electrical effects of two ion implantation approaches for dual gate oxide (DGO) formation have been examined in a sub-2 nm gate oxide, high performance complementary metal oxide semiconductor (CMOS) logic process. A masked fluorine implant prior to gate oxidation was used to control the silicon substrate oxidation rate. This process results in a simple method to precisely increase gate oxide thickness and decrease gate current in specific gate current sensitive subcircuits. The fluorine DGO methodology also produced well-behaved transistor characteristics for both thin and thicker gate oxide transistors. Using argon to produce DGO resulted in severely degraded gate oxide and transistor characteristics. Significantly higher gate current for a given oxide thickness resulted with argon implant. In addition, the argon implant produced interface states that badly degraded transistor characteristics. Transmission electron microscopy showed defect regions for the case of DGO with argon implant that was not observed with the fluorine implant. In addition, Raman scattering showed residual amorphous silicon regions with argon implantation that were not observed for the case of DGO by fluorine implantation. © 2002 The Electrochemical Society. All rights reserved.