Channel engineering using RTA prior to the gate oxidation for high density DRAM with single gate CMOS technology

Abstract

A non-uniform lateral boron profile along the channel width is observed in a buried-channel p-MOSFET and a memory cell transistor when BF 2 implantation is applied at the dose of ∼10 13 cm −2 to form a channel. SIMS profile analysis and two-dimensional simulation results show that this abnormal profile is formed by transient enhanced diffusion (TED) due to BF 2 implantation damage during gate oxidation process. It is found that RTA process just prior to the gate oxidation is useful to eliminate the TED of boron so that inverse narrow width effect, short channel effect and threshold voltage fluctuation are remarkably improved in a buried-channel p-MOSFET. In addition, the RTA process can also reduce BF 2 implantation dose without decreasing threshold voltage by the suppression of boron diffusion in a cell transistor. Therefore, the retention time of DRAM can be enhanced by reducing space charge region field in a cell transistor due to lower boron concentration compared with a conventional device.