Gate Misalignment Research Articles

Evaluation of sensitivity in a vertically misaligned double-gate electrolyte-insulator-semiconductor extended source tunnel FET as pH sensor

In this research, the primary objective is to investigate the impact of vertical gate misalignment on the source and drain regions of 30 nm. The double-gate Electrolyte-Insulated-Semiconductor extended-source Tunnel Field-Effect Transistor (ES-VTFET) is proposed for its potential application as a pH sensor. The gate electrode cannot be perfectly aligned with the channel due to fabrication tolerances, particularly in very short-channel structures. This study aims to introduce a vertical electrolyte Bio-TFET-based pH sensor capable of detecting pH changes in aqueous (electrolyte) solutions. The effect of variation in pH values on the electrical characteristics of the device such as drain current (IDS), transconductance (gm), voltage sensitivity (SV) and current sensitivity (SI) have been examined. It has been assumed that the electrolyte section is an intrinsic semiconductor material where electrons and holes signify mobile ions in aqueous solutions. The electrolyte region has an electrolyte dielectric constant of 78, an energy bandgap of 1.12 eV, and an electron affinity of 1.32 eV. Finally, the gate misalignment aspect of the proposed bio TFET-based pH sensor is emphasized by comparing sensitivity parameters. Hence, the proposed pH sensor can be used as a potential candidate for the futuristic application of biosensors.

Simulation and analysis of enhancement-mode AlGaN/GaN HEMT with P-I-N junction gate

To improve the threshold voltage and gate reliability of conventional enhancement-mode p-GaN-gated AlGaN/GaN high electron mobility transistors while maintaining a low on-resistance, an improved design solution for p-GaN HEMTs with P-I-N junction gate (PIN-HEMTs) has been proposed. Simulation results show that energy band modulation is achieved by adjusting the doping concentration and thickness of each layer of the PIN junction, and high-performance p-GaN gate HEMTs with adjustable threshold voltages ranging from 0.56 V to 4.75 V and gate breakdown voltages ranging from 19.8 V to 30.3 V would be prepared. The PIN-HEMT has a quasi-self-alignment property, which means that good gate control is independent of gate metal alignment. This not only improves the production efficiency but also solves the problems of weak gate control and electric field aggregation at the gate edge caused by the gate misalignment in conventional p-GaN gate HEMTs, thus realizing lower on-resistance and higher gate breakdown voltage, which demonstrates this proposed structure has excellent potentials for realizing effective and reliable high-power transistors.

Synergic Effect of Misaligned Gate and Temperature on Hetero‐Dielectric Double‐Gate Junctionless Metal–Oxide‐Semiconductor Field‐Effect Transistors for High‐Frequency Application

Junctionless metal–oxide‐semiconductor field‐effect transistors (MOSFETs) have emerged as a promising alternative to conventional MOSFETs, offering simplified fabrication and potential performance improvements. The novelty of this research lies in the selection of hetero‐dielectric material to optimize the performance of junctionless transistors under the misaligned gate and high‐temperature conditions, and the aim is to explore its capability for low‐power high‐frequency application. The results reveal that the proposed junctionless field effect transistor exhibits increased transconductance (17 mS), which enables higher gain (311 dB) and diminishes capacitive effects, leading to a broader range of cutoff frequencies (154 GHz) with gain frequency product and gain transconductance frequency product are 31 and 95.9 THz, respectively. Moreover, this research article investigates critical reliability issues related to junctionless MOSFET, focusing on gate misalignment and thermal stability. The study reveals that gate misalignment reduces on‐current and degrades device performance. Additionally, the study examines thermal stability over a wide temperature range (300 to 500 K), exploring the impact of temperature on performance. These valuable findings provide crucial insights to overcome fabrication challenges and drive the practical adoption of junctionless MOSFETs in future integrated circuits. To assess device performance in high‐frequency applications, Silvaco ATLAS TCAD tools are employed.

Device and circuit level performance assessments of gate engineered Ge/GaAs heterojunction doping less TFET

AbstractRecently, the doping‐less tunnel FET has gained popularity due to its lower process complexity than conventional TFETs with heavily doped source and drain regions. In this literature, we have introduced a symmetric gate Ge/GaAs heterojunction doping‐less TFET(SG HJ DL TFET) using 4.6 eV work function for both the top gate and bottom gate and an asymmetric gate Ge/GaAs heterojunction doping‐less TFET (AG HJ DL TFET) using 3.9 eV work function as top gate and 4.6 eV work function as a bottom gate. A comparative study has been performed between these two devices. The back gate misalignment engineering in the AG HJ DL TFET induces higher charge plasma near the source‐channel junction which will enhance the drain current. Due to a larger drain current, an improved ratio (11.8 times), and steeper SS (37%) are achieved in optimized AG HJ DL TFET than SG HJ DL TFET. Furthermore, the Analog/Radio Frequency and linearity performance parameters have been examined, and a significant improvement is noticed in the optimized AG HJ DL TFET. The impact of different interface trap charges (ITCs) on device performances is also investigated and it is found that AG HJ DL TFET shows more immunity to ITCs than SG HJ DL TFET. Finally, the Verilog‐A‐based model has been developed for the AG HJ DL TFET to utilize its circuit‐level behavior. The optimized device‐based Common Source amplifier (CS amplifier) has been simulated in the Cadence Virtuoso tool. The AG HJ DL TFET‐based CS amplifier offers a 6.83% improvement in voltage gain over the other reported work.

Performance assessment of charge plasma based hetero‐structure VTFET biosensor for linearity enhancement

AbstractThis paper examines a charge plasma‐based hetero‐structure full gate vertical tunnel field effect transistor (CP‐FG‐VTFET) as a dielectrically modulated biosensor. It is also compared with a charge plasma‐based short gate vertical TFET (CP‐SG‐VTFET) biosensor and a charge plasma‐based asymmetrical vertical TFET (CP‐AS‐VTFET) biosensor with identical dimensions. We examine the basic physics of these biosensors and compare their ability to recognize charged and neutral molecules. It has been noted that these designs, which use GaSb as the n‐type TFET source material, are suitable for supply voltages lower than 1.2 V. The short gate device has a lower miller capacitance and a higher drive current because it has a narrow bandgap source material. Additionally, the left and right gate alignment of asymmetrical gate architectures has a considerable impact on the sensitivity of the device. Therefore, a simulation is conducted to assess the effects of gate misalignment on biosensor surface potential and drain current sensitivity. In addition, various figures of merits (FOMs) are computed for the device utilizing the dielectric constant range of 1–12, including linearity, sensitivity, and evaluation of noise characteristics. The widely available Silvaco TCAD was employed to simulate the proposed VTFET biosensors. A comprehensive evaluation of the FOM values showed that the CP‐FG‐VTFET is a promising device in terms of linearity and sensitivity.

Impact of gate misalignment on the performance of CNTFET: TFET vs MOSFET

CNTFET device structures are gaining more research interest as conventional FET structures are reaching their scaling limits. One of the most crucial effects that could occur in the fabrication on the nanometer scale is the gate misalignment. In this paper, we report on a study of the impact of gate misalignment on the performance of MOSFET and TFET CNT-based device architectures. Given the fact that gate misalignment can occur on any side of the gate, extensive simulations have been carried out to account for the gate misalignment towards the source and the drain sides. We scrutinize how the misalignment influences the device performance parameters like ON-current, subthreshold swing SS, overall gate capacitance and cut-off frequency. Moreover, these “Figure of Merits” are calculated for two cases, one of which uses a single oxide all over the device various regions and the other incorporates a low-k oxide spacer material over the source and the drain regions while a high-k gate oxide material is utilized over the channel region. Simulation results show that MOSFETs are more immune to the fabrication process variations than TFETs.

Study of digital/analog performance parameters of misaligned gate recessed double gate junctionless field-effect-transistor for circuit level application

In this work, the effect of gate misalignment towards the source and drain ends for 20 nm recessed double gate junctionless field-effect-transistor (R_DGJLFET) have been studied on various digital and analog performance parameters from device to circuit level while setting the simulation set-up using 2D Silvaco ATLAS technology computer aided design (TCAD). With recessed silicon channel, the quantum confinement effects have been considered for channel thickness <7 nm. In comparison to conventional double gate junctionless FET (C_DGJLFET), the device exhibits lesser OFF-current, improved ON-to-OFF current ratio, better subthreshold slope (SS), and lower drain-induced-barrier-lowering (DIBL). Analogically, it has been found that the misaligned gate towards drain affects the digital and analog parameters more severely in comparison to gate misalignment towards the source end. However, the misaligned R_DGJLFET towards the drain end shows robustness in terms of SS and DIBL with smaller variations of ∼10.84% and ∼61.79%, respectively. Moreover, due to very low parasitic capacitances, the device shows lesser variations in different alternating current (AC) performance parameters namely, transconductance generation factor (TGF), unity gain frequency, and gain-bandwidth product in comparison to C_DGJLFET. With gate misalignment towards source the unity gain frequency, and gain-bandwidth improve by ∼9.67% and ∼19.9%, respectively whereas the TGF remains almost unaffected. Furthermore, to ensure the device capability in circuit application a complementary metal-oxide-semiconductor (CMOS) inverter and common-source (CS) amplifier based on R_DGJLFET have been designed. In contrast to C_DGJLFET based counterpart, the R_DGJLFET expresses its suitability for low-power digital applications with better noise margins and smaller short-circuit current in the CMOS inverter. In analog domain, the R_DGJLFET based CS amplifier shows an improved amplification factor of 4.75 in comparison to C_DGJLFET. This paper provides deep insight into the severity of gate misalignment towards source/drain for R_DGJLFET in both digital and analog domains from device to circuit level.

Design and Performance Analysis of Symmetrical and Asymmetrical Triple Gate Dopingless Vertical TFET for Biorecognition

The present paper proposes a dielectric modulation based Triple Gate Doping Less Tunnel Field Effect Transistor (TG-DLTFET) biosensor with a cavity introduced underneath the gate and source metal for symmetrical and asymmetrical device to recognize very small size biomolecules such as Amino Acids (AAs). The proposed n + pocket doped vertical device aims to achieve high sensitivity with lower short channel effects. The placement and width of the n + pocket layer within the source are reformed with the goal of acquiring the higher current switching ratio. The variation in the device’s electrical parameters (surface potential, drain current and sensitivity) corresponding to dielectric constant and charge density reflected the biorecognition process in the biosensor. Additionally, the impact of variations in device geometry (spacer length, cavity length, cavity thickness, and gate misalignment effects) on the drain current and drain current sensitivity of device have also been evaluated and reasoned, respectively. The results reflect that with proper choice of the geometric parameters, the device sensitivity can be attained up to 1010. Thus, the present findings reflected that TG-DLTFET has a better sensing capability as a biosensor, together with a low value of short channel effect and leakage current. The proposed n + pocket doped vertical device has a significant potential to detect varations in AAs and DNA.

Impact of Left Side Back Gate Misalignment Effect in an Analytical Tunneling Current Modeling of an Ultrathin Asymmetric DG TFET

This paper exhibits a detailed explanation of an analytical band to band tunneling current model with gate misalignment effect for an ultrathin n type Asymmetric DG TFET considering fringing effect on the non gate overlapping channel region formed due to left side shifting of back gate. Model includes leakage current around the channel-drain interface, has a great impact in sub-threshold region and verified under front gate voltage with gate length scaled to 20 nm for different back gate shifts and various back gate voltages with Silicon Dioxide (SiO2) as gate insulator. It also exhibits a good concurrence with the device simulator in representing drain voltage dependent tunneling current characteristics with different front gate voltages. We authenticate our model throughout several simulations comparing device simulator ISE TCAD results and exhibits an excellent correlation.

Design and analysis of dual-gate misalignment on the performance of dopingless tunnel field effect transistor

The submitted work presents a designed and analyzed dopingless double-gate tunnel field effect transistor. In the designed dopingless structure, doping is introduced by charge plasma technique and silicon is used as a choice of material. Initially, gate misalignment was done by shifting the bottom gate away from the drain region and toward the drain region by 50% and 100% amount. Further, both gates (top and bottom) have been misaligned by 50% and 100% for analyzing the device for analog and linearity performance. Analog parameters, device parameters and linearity parameters were calculated in order to understand the device behavior. By misaligning gates, it is found that when the bottom gate is shifting away from the source region, both gates have been misaligned by 100% showing that analog and linearity performance of the devices degrades. When the bottom gate is shifted toward the source, both gates have been misaligned by 50% providing better analog and linearity performance. Among all the misaligned structures, when both gates have been misaligned by 50% gives the best result such as ON-state current, OFF-state current, ION/IOFF, and subthreshold slope are 2.3 µA, 5.07 aA, 4.5 × 1011 and 32 mV/decade respectively.

Impact of core thickness and gate misalignment on rectangular core–shell based double gate junctionless field effect transistor

A rectangular core is inserted in double gate junctionless transistor (DGJLT) which separates the top shell and bottom shell in the device called as rectangular core–shell double gate junctionless transistor (RCS-DGJLT). The core doping and core thickness are optimized to improve the performance of RCS-DGJLT. The core thickness is optimized for different shell thicknesses in the device which has not been explored yet in the literature. An interesting observation is found that the core thickness should be equal to the shell thickness for smaller shell thicknesses, whereas the thicker core is required for larger shell thicknesses. RCS-DGJLT has shown remarkable improvement than DGJLT. Further, the effect of gate misalignment on either side (source/drain) of the channel in RCS-DGJLT and DGJLT is studied and compared on the basis of device performance. The study of gate misalignment becomes essential due to the complications on achieving perfectly aligned gates during the fabrication of double gate device. An RCS-DGJLT is found to have better tolerance to gate misalignment than DGJLT. The best parametric values like OFF current is ∼10–16A, ON current is ∼10–5A, subthreshold slope is nearly 66.2 mV/decade, ON/OFF current ratio is ∼1010, drain induced barrier lowering is ∼42.1 mV V−1 and threshold voltage ∼0.56 V at perfectly aligned gate condition is obtained on keeping core and shell thickness at 3 nm each. As per the analysis, the gate misalignment up to 20% on either side of the channel does not impact the performance parameters much and hence reduces the stress of meeting the requirement of perfect gate alignment.

Gate misalignment effects on analog/RF performance of charge plasma-based doping-less tunnel FET

In this paper, gate misalignment effect on charge plasma-based doping-less tunnel FET (DLTFET) is demonstrated for the first time. The effects of bottom gate misalignment on either towards source (GMAS) or towards drain (GMAD) are then compared with the conventional doped TFET (DGTFET). This paper also discusses the effect of misalignment on the bases of different analog/RF parameters such as transconductance (gm), output conductance (gd), intrinsic gain (AV), total gate capacitance (Cgg), and cut-off frequency (fT). When bottom gate is misaligned towards source, DLTFET provides a better performance than DGTFET and shows the best results when the device is 50% misaligned. While gate misalignment towards drain, both devices show similar performance and degrade with the increase in misalignment. The DLTFET is found to have a better tolerance to the different misalignment configurations than DGTFET.

Reliability analysis of Junction-less Double Gate (JLDG) MOSFET for analog/RF circuits for high linearity applications

Junctionless double gate (JLDG) MOSFET in sub nano meter regime has been the preferred choice for researchers as the leakage current in a JLDG MOSFET is significantly less compared to junction based double gate (DG) MOSFET. Also since the conduction mechanism in JLDG MOSFET is bulk conduction instead of surface channel conduction, the short channel effects (SCEs) get significantly reduced. In this research paper, major reliability issues concerning JLDG MOSFET has been studied and discussed. This research paper considers the gate misalignment effect and analysis of the thermal stability by subjecting the temperature variation from 200K to 500K. Gate misalignments is one of the major reliability issues and with enhancement in second order effects, it causes reduction in on current that degrades the performance of a JLDG MOSFET. The alignment between front and back gate critically influences the performance of a JLDG device. Misalignment effect in the device occurs due to shift in the back gate either towards the drain side or the source side. The gate misalignment therefore introduces some non-ideal effects from overlap or non-overlap regions. Thermal stability of the device has been tested for operating the device over a wide range of temperatures ranging from 200K to 500K, so that the effect of temperature on the performance issues remains limited. Further, the analog/RF performance parameters have been evaluated and linearity distortion analysis due to gate misalignment effect in terms of major performance matrices has been investigated. The investigated results show that there exist a thermally stable point in and around which if the device operates would be more stable.

Transforming gate misalignment into a unique opportunity to facilitate steep switching in junctionless nanotransistors

In this work, we examine the feasibility of triggering impact ionisation at sub-bandgap voltages through optimal utilisation of structural non-ideality induced electric field redistribution in the semiconductor film for an energy efficient steep switching junctionless (JL) transistor. While misalignment between front and back gates is often considered as a disadvantage due to loss of gate controllability, the work highlights its usefulness and applicability in nanoscale devices to engineer the electric field to enhance the product of current density (J) and electric field (E) and activate impact ionisation at sub-bandgap applied voltages. Results show that intentionally misaligned gates in silicon and germanium based JL devices exhibit an inclined conduction channel and achieve a nearly ideal value of steep subthreshold swing (∼ 1 mV decade−1) at room temperature. The work provides new viewpoints to realise energy efficient JL devices through the sharp increase of drain current from off-state to on-state achieved due to intentional misalignment between front and back gates.

Improving retention time in tunnel field effect transistor based dynamic memory by back gate engineering

In this work, we report on the impact of position, bias, and workfunction of back gate on retention time of Tunnel Field Effect Transistor (TFET) based dynamic memory in ultra thin buried oxide and Double Gate (DG) transistors. The front gate of the TFET is aligned at a partial portion of the semiconductor film and controls the read mechanism based on band-to-band tunneling. The back gate is engineered to improve the performance of the dynamic cell by positioning it at the region uncovered by the front gate where it forms a deep potential well. The physical well formed by the back gate misalignment is made more profound by using a p+ poly workfunction as it accumulates more holes in the storage region and forms a deep potential well that sustains holes for longer duration, thereby increasing the retention time. The retention time is also governed by the generation and recombination phenomenon which can be controlled through the applied bias at the back gate. The retention time attained is ∼2 s at a temperature of 85 °C through optimal back gate engineering in DG transistors. The work shows innovative viewpoints of transforming gate misalignment, traditionally considered detrimental into a unique opportunity, coupled with appropriate selection of back gate workfunction and bias to significantly improve the retention time of capacitorless dynamic memory.

Parasitic-Aware Common-Centroid FinFET Placement and Routing for Current-Ratio Matching

The FinFET technology is regarded as a better alternative for modern high-performance and low-power integrated-circuit design due to more effective channel control and lower power consumption. However, the gate-misalignment problem resulting from process variation and the parasitic resistance resulting from interconnecting wires based on the FinFET technology becomes even more severe compared with the conventional planar CMOS technology. Such gate misalignment and unwanted parasitic resistance may increase the threshold voltage and decrease the drain current of transistors. When applying the FinFET technology to analog circuit design, the variation of drain currents can destroy current-ratio matching among transistors and degrade circuit performance. In this article, we present the first FinFET placement and routing algorithms for layout generation of a common-centroid FinFET array to precisely match the current ratios among transistors. Experimental results show that the proposed matching-driven FinFET placement and routing algorithms can obtain the best current-ratio matching compared with the state-of-the-art common-centroid placer.

The impact of gate misalignment on the analog performance of a dual-material double gate junctionless transistor

The analog performance of gate misaligned dual material double gate junctionless transistor is demonstrated for the first time. The cases considered are where misalignment occurs towards source side and towards drain side. The analog performance parameters analyzed are: transconductance, output conductance, intrinsic gain and cut-off frequency. These figures of merits (FOMs) are compared with a dual material double gate inversion mode transistor under same gate misalignment condition. The impacts of different length of control gate (L1) for a given gate length (L) are also studied and the optimum lengths L1 under misalignment condition to have better analog FOMs and high tolerance to misalignment are presented.

Analog performance investigation of misaligned double gate junctionless transistor

In this paper, the analog performance of a misaligned double gate junctionless transistor (DGJLT) is demonstrated for the first time. The gate misalignment can occur on either source side (MA_S) or at drain side (MA_D). Since misalignment is a type of degradation that occurs during device fabrication, the idea behind this demonstration is to analyze the impact of gate misalignment on DGJLT. The analog performance parameters analyzed are, transconductance $$(\hbox {g}_{\mathrm{m}})$$(gm), output conductance $$(\hbox {g}_{\mathrm{ds}})$$(gds), early voltage $$(\hbox {V}_{\mathrm{EA}})$$(VEA) and intrinsic gain $$(\hbox {A}_{\mathrm{VO}})$$(AVO). They are compared with a double gate inversion mode transistor (DGIMT) under same gate misalignment condition. A DGJLT is found to have better tolerance to gate misalignment compared to DGIMT. MA_S configuration of a DGJLT shows better analog performance compared to MA_D configuration where as for DGIMT it shows better performance for MA_D compared to MA_S configuration.

Impact of gate coupling and misalignment on performance of double-gate organic thin film transistors

This paper proposes a numerical simulation of the dual-gate organic thin film transistors (DG-OTFTs). It is revealed that electrically separable double-gate architecture is able to dynamically control the threshold voltage by the coupling of the top/bottom gates. We also observe that the device characteristics are sensitive to the misalignment and the moving direction between top/bottom gates. A significant change to the driving ability and threshold voltage is found while misalignment exists. As the misalignment is larger, the driving-current reduces and threshold voltage increases quickly. Also the degradation is severe while the mismatch is moved to drain and relaxed with large channel length.

Performance Analysis of Gate Misaligned Triple Material Double Gate (TMDG) MOSFET

In the literature, the misalignment effects in a nanoscale MOSFETis analyzed for dual material Double gate MOSFET. The analysis is used in the design criterion of the device. In this paper, a two dimensional analytical model of gate misalignment effects in Triple Material Double Gate (TM -DG) MOSFET is presented for the first time. The gate misalignment effect in the drain side is considered. Based on the misaligned gate, the device is split in to six regions. The boundary conditions are obtained considering the electric flux and the potential. The parameters are deriv ed using region based approach. Parameters like surface potential and electric field is studied. In general various methods like superposition method, Fourier series method, Numerical methods are used to analyze the device. In our paper, the parabolic approximation method is used for analytical modeling of TM -DG MOSFET since it is more accurate than the other methods available in the literature. The results are simulated and compared with dual material double gate MOSFET. The device performance is analyzed and it helps in the design scenario.