Impact of gate misalignment on the performance of CNTFET: TFET vs MOSFET

Abstract

CNTFET device structures are gaining more research interest as conventional FET structures are reaching their scaling limits. One of the most crucial effects that could occur in the fabrication on the nanometer scale is the gate misalignment. In this paper, we report on a study of the impact of gate misalignment on the performance of MOSFET and TFET CNT-based device architectures. Given the fact that gate misalignment can occur on any side of the gate, extensive simulations have been carried out to account for the gate misalignment towards the source and the drain sides. We scrutinize how the misalignment influences the device performance parameters like ON-current, subthreshold swing SS, overall gate capacitance and cut-off frequency. Moreover, these “Figure of Merits” are calculated for two cases, one of which uses a single oxide all over the device various regions and the other incorporates a low-k oxide spacer material over the source and the drain regions while a high-k gate oxide material is utilized over the channel region. Simulation results show that MOSFETs are more immune to the fabrication process variations than TFETs.