Abstract
This paper exhibits a detailed explanation of an analytical band to band tunneling current model with gate misalignment effect for an ultrathin n type Asymmetric DG TFET considering fringing effect on the non gate overlapping channel region formed due to left side shifting of back gate. Model includes leakage current around the channel-drain interface, has a great impact in sub-threshold region and verified under front gate voltage with gate length scaled to 20 nm for different back gate shifts and various back gate voltages with Silicon Dioxide (SiO2) as gate insulator. It also exhibits a good concurrence with the device simulator in representing drain voltage dependent tunneling current characteristics with different front gate voltages. We authenticate our model throughout several simulations comparing device simulator ISE TCAD results and exhibits an excellent correlation.
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