Abstract
In this paper, the analog performance of a misaligned double gate junctionless transistor (DGJLT) is demonstrated for the first time. The gate misalignment can occur on either source side (MA_S) or at drain side (MA_D). Since misalignment is a type of degradation that occurs during device fabrication, the idea behind this demonstration is to analyze the impact of gate misalignment on DGJLT. The analog performance parameters analyzed are, transconductance $$(\hbox {g}_{\mathrm{m}})$$(gm), output conductance $$(\hbox {g}_{\mathrm{ds}})$$(gds), early voltage $$(\hbox {V}_{\mathrm{EA}})$$(VEA) and intrinsic gain $$(\hbox {A}_{\mathrm{VO}})$$(AVO). They are compared with a double gate inversion mode transistor (DGIMT) under same gate misalignment condition. A DGJLT is found to have better tolerance to gate misalignment compared to DGIMT. MA_S configuration of a DGJLT shows better analog performance compared to MA_D configuration where as for DGIMT it shows better performance for MA_D compared to MA_S configuration.
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