Gate-induced Drain Leakage Research Articles

Impact of source/drain lateral straggle on GIDL current of low SS NC-FinFET

ABSTRACT In this paper, the gate-induced drain leakage (GIDL) issue in negative capacitance (NC-FinFET) has been comprehensively addressed using Sentaurus 3-D TCAD simulations. Incorporation of ferroelectric (FE) materials in the gate stack of NC-FinFET increases with current by 12% compared to that of baseline FinFET. A steeper sub-threshold swing (SS) of 8 mV/dec is achieved at a FE-thickness of 5 nm at a lateral straggle; (σ) = 0 nm. GIDL behaviour with respect to the variation of source/drain σ and gate oxide thicknesses of NC-FinFET with and without the presence of the GateTunneling model is thoroughly investigated. Investigations demonstrate that in NC-FinFET, there are steeper energy band profiles near source/drain owing to coupling of fringing fields to the ferroelectric layer, which exhibits a larger and prior commencement of the longitudinal band to band tunnelling current compared to conventional FinFET. Moreover, the effect of variation of σ on various parameters viz. SS, capacitance and transconductance has also been investigated, which shows better results for lower σ values. At σ = 0 nm, drain-induced barrier lowering is −187.23 mV/V as compared to that of σ = 5 nm, which is −355.3 mV/V. Furthermore, we have also investigated drain current noise spectral density (SID) and gate voltage noise spectral density (SVG) with respect to fin width (WFIN) at the optimised σ value.

A comprehensive study of gate-induced drain leakage current and electrical characteristics in nanosheet field-effect transistors due to variation in structural parameters and ambient temperature

Abstract IIn this paper, two substrate optimization approaches of triple stacked Nanosheet FET (SNSHFET), namely optimization of buried oxide and selective deposition of punch through stopper (PTS) substrate, have been examined and simulations have been carried out using Technology Computer-Aided (TCAD) software. A comprehensive study of leakage current and key electrical characteristics (I¬ON, VT, SS, DIBL) have also been extracted based on variation in temperature from 298 K to 450 K, sheet width, fin pitch, substrate width, and source/drain doping, as well as different substrates. When the ambient temperature of SNSHFET is varied from 298 K to 450 K, the gate-induced drain leakage (GIDL) current increases and degrades the VT and ION/IOFF ratio. GIDL current also increases with increased doping of the source and drain. Also, the impact of ultra-thin body substrate in SNSHFET is studied for the reduction in GIDL current and optimization in the performance. It is observed that a reduction in the substrate width and the nanosheet width decreases the GIDL current, while variation in Inter-fin pitch has no significant impact on the GIDL current and other electrical characteristics. The band-to-band tunneling rate and electric field profiles are observed at the channel-drain and gate-substrate overlap region for understanding the physical insights of leakage current in the SNSHFET. This work also answers the dependency of GIDL current on the gate and drain voltage supply respectively. In addition to that, how GIDL current responds to the variation in the source-drain doping and with different PTS doping has been explained. The 3 nm-based SNSHFET is designed and its electrical and GIDL characteristics are compared with novel devices like Forksheet FET and Complementary FET.

Simulation of different structured gate-all-around FETs for 2 nm node

This paper compares different types of Gate All Around (GAA) FET structures using TCAD simulation, including Lateral Nanosheet, Lateral Nanowire, Vertical Nanosheet, and Vertical Nanowire. The increase in electrostatic control and reduced short channel effects are key benefits to adopting GAAFET structures to meet scaling requirements for next generation process nodes. To understand channel geometry impacts on performance, the channel effective width (Weff) is swept around the projected dimensions, including ratio of height and width parameters. The performance is evaluated using the key device metrics such as on-state current (Ion), off-state current (Ioff), and threshold voltage (Vt) for transfer characteristics, and drain-induced barrier lowering (DIBL), subthreshold slope (SS), and gate induced drain leakage (GIDL) for short-channel effects. It is observed that thinner channel geometries, as often seen implemented in Nanosheet structures, have major benefits across SCE and Ioff metrics compared to more symmetrically square shaped channels. Additionally, stacking channels as a means to increase Weff appears to be an attractive option for increasing performance without significant increase in SCEs observed. For bulk technology the ratio between height and width of a Nanosheet structure can be optimized to reduce parasitic channel influence, so that optimal Ion/Ioff ratio is achieved.

Performance enhancement of nanotube junctionless FETs with low doping concentration rings

To reduce the static power consumption of the NT JLFET and the effect of SCEs on the NT JLFET, A nanotube junctionless field effect transistor with cyclic low doping concentration regions (C NT JLFET) is proposed. Based on Sentaurus TCAD numerical simulations, the electrical properties of the C NT JLFET and the NT JLFET were comparatively investigated, and the effects of the length (L CD) and radius (R CD) of cyclic low doping concentration regions on the electrical properties of the C NT JLFETs were studied. The C NT JLFET reduces the gate-induced drain leakage (GIDL) due to lateral band-to-band-tunneling (L-BTBT) as compared to the NT JLFET. As the L CD or R CD increases, the off-state current decreases. In addition, the C NT JLFET suffers from fewer short channel effects (SCEs), such as threshold voltage roll-off, drain-induced barrier lowering and subthreshold swing deterioration, compared to the NT JLFET. The inhibition of L-BTBT and attenuation of SCEs by cyclic low doping concentration regions remains when the channel length of the C NT JLFET is shortened to 10 nm. The C NT JLFET are suitable for low power applications as they exhibit reduced L-BTBT and suffer from fewer SCEs.

6‐1: Pragmatic low‐temperature polycrystalline thin‐film transistor technologies for high‐brightness and high‐temperature environments in AMOLED displays

This paper presents experimental and theoretical analysis of electrical characteristics for recent process‐based low‐temperature polysilicon (LTPS) thin‐film transistors (TFTs) in AMOED displays, focusing on high‐temperature and high‐luminance device characteristics. All off‐state current (Ioff) components in such conditions, which include gate‐induced drain leakage (GIDL), thermal generation, photo generation currents, are in detail analyzed. Exploring the effects of process technologies and device design in small‐size TFTs, in conjunction of reduced defect density‐of‐state (DOS) in the polycrystalline and its interface of gate oxide, we investigate optimal device and process design for reliable polycrystalline thin‐film transistor technologies in high‐brightness and high‐temperature situations. Numerical device simulations, supplemented by physics‐based analysis, confirm experimental results for our optimized device/process and gain diligent process/ design co‐optimization insights.

Computational modelling of cylindrical-ferroelectric-dual metal-nanowire field effect transistor (C-FE-DM-NW FET) using landau equation for gate leakage minimization

In order to address and resolve the significant problem of gate-induced drain leakage (GIDL) current and enhance device reliability, band-to-band tunnelling (BTBT), and OFF-state leakages, a computational model of a cylindrical-ferroelectric-dual-metal-nanowire-field effect transistor (C-FE-DM-NW-FET) has been proposed in this manuscript. The proffered structure is a symmetric gate structure with ferroelectric layer sandwiched between the gate terminal and oxide layer which reduces the BTBT which in term reduces the OFF-state leakage hence making the device definitive for low power applications. In this manuscript, there has been a reduction in the leakage current by a magnitude of 104 times in 50 nm and 107 times in 60 nm channel length which translates to a reduction in gate leakage (IGIDL) of more than 100 % in C-FE-NW-FET over C-NW FET. To analyze the Electric Field, Surface Potential, and IGIDL with the proper boundary conditions, the 2D Poisson's equation is solved analytically with Landau-Khalatnikov (LK) equation. The analytical findings are quite similar to the simulated outcomes.

Modeling of inner-outer gates and temperature dependent gate-induced drain leakage current of junctionless double-gate-all-around FET

In this paper, the temperature-dependent gate-induced drain leakage (GIDL) current model is proposed with the help of a lateral electric field (EL) across the inner and outer gate interfaces of the junctionless double-gate-all-around (JL-DGAA) field-effect transistor (FET). The EL at the interface is obtained from the surface potential equation after solving the 3D Poisson equation with appropriate boundary conditions. The derived model is validated using the well-calibrated TCAD simulator platform with experimental data. A higher GIDL current at the outer gate-channel interface is observed compared to the inner gate-channel interface in the OFF-state conditions due to the high EL between the channel and drain, which is reported for the first time here. The effect of temperature (from 200 K to 500 K) on the GIDL current is also observed, which increases linearly with increasing temperature. Further, the impact of induced mechanical stress (MS) is investigated on the GIDL current, where the GIDL current increases exponentially with increasing induced MS due to effective mass and band gap reduction. Finally, the dynamic performance is investigated in terms of the gate delay time as a function of channel length and temperature. The gate delay diminishes with decreasing channel length and increasing temperature, which shows the switching speed and ability of the device.

Parameteric optimization of SiGe S/D NT JLFET using analytical modeling to improve L‐BTBT induced GIDL

AbstractIn the present work, we investigate the impact of structure dimensional parameters on the short channel effects which occurs especially below 20 nm regime particularly gate induced drain leakage (GIDL) current. Using technology computer aided design simulation (TCAD), we have examined the GIDL for SiGe as source/drain in NTJLFET. The structural dimensional parameters such as the nanotube thickness, core and outer gates thickness and gate electrode work function shows the significant impact on the band to band tunneling in lateral direction (L‐BTBT) which induced GIDL current. It is analyzed that increase in the nanotube thickness and physical oxide thickness increase the GIDL current, while increasing the gate electrode work function, core gate and outer gate thicknesses gives reduced GIDL current. The SiGe S/D NTJLFET produce a remarkable high ION/IOFF ratio ~ 1011. A compact model for GIDL current is also developed which shows the dependency of structure parameters on leakage current. The SiGe has been incorporated as source and drain in NTJLFET which creates the energy band discontinuity. Furthermore, SiGe S/D NTJLFET is fairly compared with the conventional NT JLFET and nanowire (NW) JLFET and shows an improved performance.

The Optimization of Program Operation for Low Power Consumption in 3D Ferroelectric (Fe)-NAND Flash Memory

This paper proposes an optimized program operation method for ferroelectric NAND (FE-NAND) flash memory utilizing the gate-induced drain leakage (GIDL) program and validated through simulations. The program operation was performed by setting the time for the unselected cell to reach the pass voltage (Vpass) to 0.1 µs, 0.2 µs, and 0.3 µs, respectively. As the time for the unselected word line (WL) to reach Vpass increases, the channel potential increases due to a decrease in the electron–hole recombination rate. After the program operation, the threshold voltage (Vth) shift of the selected cell and the pass disturb of the unselected cells according to the Vpass condition were analyzed. Consequently, there was a more significant change in Vth among selected cells compared to the time for unselected cells to reach Vpass as 0.1 µs. The findings of this study suggest an optimal program operation that increases slowly and decreases rapidly through the variation of Vth according to the program operation. By performing the proposed program operation, we confirmed that low-power operation is achievable by reducing the WL voltage by 2 V and the bit line (BL) voltage by 1 V, in contrast to the conventional GIDL program.

Mechanism study of Hot Carrier Degradation Recovery by Gate Induced Drain Leakage in 14nm n FinFET

Mechanism study of Hot Carrier Degradation Recovery by Gate Induced Drain Leakage in 14nm n FinFET

A Novel Read Scheme Using GIDL Current to Suppress Read Disturbance in 3-D nand Flash Memories

In this paper, a novel read scheme using gate-induced drain leakage (GIDL) current is proposed to suppress read disturbance in 3-D NAND flash memories. The proposed read scheme is demonstrated through the technology computer-aided design (TCAD) simulation. In the selected string, GIDL current is not generated due to the low potential difference. On the other hand, in the unselected string, holes are accumulated under the selected cell and potential of the selected cell is enhanced due to the GIDL current before the read operation. The potential differences between the selected and adjacent cells are decreased and maximum electric field (Em) is decreased. Therefore, soft programming in the selected cell during the read operation is decreased and hot carrier injection (HCI) between selected and adjacent cells is reduced completely. The proposed read scheme can be applied to high stacked WL layers over 200 layers.

Voltage scheme for string-select transistors to improve inhibition characteristics during 1-bit erase in vertical NAND flash

We propose a new voltage scheme for string-select (SS) transistors to improve inhibition characteristics of unselected cells during selective 1-bit erase in vertical NAND flash memory. Different from the reported schemes, we apply different control voltages to each of the three SS transistors of unselected drain select lines and all source select lines to lower the channel potential. The change in the channel potential depending on the voltage of the SS transistors and the resulting gate-induced drain leakage is explained via TCAD simulation. The proposed pulse method can reduce the Vth of the 1-bit cell selected for erase by 168% compared to the reported method while maintaining the same inhibition characteristics.

Based on the comparisons with various types of transistors to predict the trend of nanotube FETs in the future

With the improvement of new technology in electronic devices and the development of nanomaterials, higher better device performance and more efficient functions of Field-Effect Transistors (FETs) are expected, these require the use of material that has well-performed physical and chemical properties. Carbon nanotubes are a viable alternative, and their popularity is increasing rapidly in recent years. With the decrease in the size of the transistor, the increase in current, and the strength of magnetic and electrical fields, many problems for the creation of destructive and leaky currents occurred. This article mainly aimed to summarize three main FET types and included new carbon nanotube FETs by introducing their basic working mechanism and discussing the difficulties such as the short channel effect, gate-induced drain leakage and contact resistance. It also tries to give a few possible solutions to them which include adding a Lightly Doped Drain or using chemical doping, as well as predict how the potential of FETs in the future at the end.

Experimental assessment of gate-induced drain leakage in SOI stacked nanowire and nanosheet nMOSFETs at high temperatures

This paper presents an experimental assessment of gate-induced drain leakage (GIDL) in stacked nanowire and nanosheet transistors for different temperatures of operation, in the temperature range between 300 K and 580 K. The temperature rise increases the GIDL current and its dependence on the device width due to the increase of band-to-band generation with temperature and weakening of electrostatic coupling.

Investigating DC and AC degradation behaviors to P-type low temperature polycrystalline silicon thin film transistor with fin-like structure

Currently, thin film transistor (TFT) based on planar structure is widely used in the applications of display panels. However, when the device is scaling-down, new device structures or novel materials should be introduced. In this work, the low temperature polycrystalline silicon (LTPS) TFT with fin-like structure is investigated. On the basis of electrical measurements, the device features good switching characteristics with low operating voltages. However, the I d–V g sweeping result exhibits off-state leakage, which is known as the gate-induced drain leakage (GIDL) current. The GIDL current is increased with the drain bias and the temperature increasing. To observe the GIDL current degradations, different gate biases with negative bias stress and positive bias stress are applied. The results show different degradation behaviors. In addition, bias stresses with DC and AC methods are also applied to verify the device reliability. Both threshold voltage (V t) shift and sub-threshold swing (S.S.) are also extracted to verify the degradations of the device. Finally, the physical models are also proposed to illustrate the degradation behaviors of the LTPS device with a fin-like structure, which can be beneficial to future related development of LTPS-based devices.

Comprehensive study of gate induced drain leakage in nanowire and nanotube junctionless FETs using Si1-xGex source/drain

We present, in this paper, optimized nanotube (NT) and nanowire (NW) junctionless field-effect transistor (JLFET) architectures of gate-induced drain leakage (GIDL). At the source/ drain–channel interface, SiGe creates a valence energy band discontinuity which alleviates lateral band-to-band tunneling (L-BTBT) of electrons in the OFF-state. It is established through 2-D TCAD simulations that inclusion of SiGe decreases L-BTBT in the NTJLFET by >5 orders, thus leading to a substantial ION/IOFF of with precision 1012 for a 20 nm gate length which is not attainable in the conventional NTJLFET (ION/IOFF ∼ 106). Furthermore, degraded OFF-state current in NWJLFET because of conventional charge-sharing effect improves with the inclusion of SiGe by ∼2 orders of magnitude. Additionally, it is effective to place SiGe layers positioned at the source and drain regions and SiGe/ Si interface inside or at the channel region. Based on the proposed design guidelines, we show that the optimized SiGe S/D NTJLFET is effective in reduction of L-BTBT GIDL when gate length is scaled to 5 nm.

Design impact on three gate Dynamic Flash Memory (3G_DFM) for long hole retention time and robust disturbance shield

TCAD simulation using Silvaco software has shown that the 3G_DFM, which has SG1 (Select Gate 1), PL (Plate Line Gate), and SG2 (Select Gate 2) between SL (Source Line) and BL (Bit Line), has a long retention time of 100ms at 85 °C, and a robust disturbance shield which is a thousand times BL stress. The two select gates SG1 and SG2 protect the recombination of holes in the FB (Floating Body) at the SL and BL pn-junctions, and shield the BL stress arising during other page operations, which leads to the GIDL (Gate Induced Drain Leakage) current.

Winner-Takes-All Neural Network Based on 3D NAND Flash With 1-Bit Erase Scheme

3D NAND flash memory constitutes strong competitors for neuromorphic computing due to its high density and mature technology. Neural networks based on 3D NAND flash differential pair have been reported since conventional block erase scheme hinders individual conductance modulation. However, the differential pair scheme halves the efficient synaptic density and erase operation is still inevitable when one of the pair devices reaches its minimum conductance. To overcome these shortcomings, the 1-bit erase scheme was proposed based on gate induced drain leakage (GIDL) effect. But in this scheme, there are risks in unintended erase. In this work, gradient bias is adopted to eliminate the potential risks in the 1-bit erase scheme. Both TCAD simulation and experimental results manifest better inhibition of unintended erase. Based on this improved scheme, a winner-takes-all neural network is constructed, where the efficient synaptic density is doubled and free from the minimum conductance dilemma in previous work based on differential pair scheme.

A Novel Charge Pumping Technique With Gate-Induced Drain Leakage Current

A Novel Charge Pumping Technique With Gate-Induced Drain Leakage Current

Investigation of Gate Induced Drain Leakage in Nanotube and Nanowire: A Comprehensive Study

In this paper, a comprehensive study of gate-induced drain leakage (GIDL) in conventional silicon-nanotube (Si-NT JLFET), SiGe Source/Drain silicon-nanotube junctionless field effect transistor (S/D Si-NT JLFET) and conventional nanowire (NW) have been performed using technology computer-aided design simulations. We have also demonstrated that inclusion of SiGe S/D in Si-NT JLFET reduced the OFF-state current by order of [Formula: see text]3 from NT JLFET and by order of [Formula: see text]6 from NW JLFET. The impact of variation of core gate thickness ([Formula: see text], germanium (Ge) content [Formula: see text], and location of SiGe in source and drain regions of the S/D Si-NT JLFET have been studied from the GIDL perspective. We found that SiGe S/D Si-NT JLFET exhibits impressively high [Formula: see text]/[Formula: see text] ratio [Formula: see text]10[Formula: see text] with reduced lateral band-to-band tunneling (L-BTBT)-induced GIDL than the conventional nanowire device. The is due to SiGe S/D that creates a energy valence band discontinuity at source drain interfaces which limits the flow of electrons from channel to drain region in the OFF-state.