Abstract

In order to address and resolve the significant problem of gate-induced drain leakage (GIDL) current and enhance device reliability, band-to-band tunnelling (BTBT), and OFF-state leakages, a computational model of a cylindrical-ferroelectric-dual-metal-nanowire-field effect transistor (C-FE-DM-NW-FET) has been proposed in this manuscript. The proffered structure is a symmetric gate structure with ferroelectric layer sandwiched between the gate terminal and oxide layer which reduces the BTBT which in term reduces the OFF-state leakage hence making the device definitive for low power applications. In this manuscript, there has been a reduction in the leakage current by a magnitude of 104 times in 50 nm and 107 times in 60 nm channel length which translates to a reduction in gate leakage (IGIDL) of more than 100 % in C-FE-NW-FET over C-NW FET. To analyze the Electric Field, Surface Potential, and IGIDL with the proper boundary conditions, the 2D Poisson's equation is solved analytically with Landau-Khalatnikov (LK) equation. The analytical findings are quite similar to the simulated outcomes.

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