Modeling of inner-outer gates and temperature dependent gate-induced drain leakage current of junctionless double-gate-all-around FET

Abstract

In this paper, the temperature-dependent gate-induced drain leakage (GIDL) current model is proposed with the help of a lateral electric field (EL) across the inner and outer gate interfaces of the junctionless double-gate-all-around (JL-DGAA) field-effect transistor (FET). The EL at the interface is obtained from the surface potential equation after solving the 3D Poisson equation with appropriate boundary conditions. The derived model is validated using the well-calibrated TCAD simulator platform with experimental data. A higher GIDL current at the outer gate-channel interface is observed compared to the inner gate-channel interface in the OFF-state conditions due to the high EL between the channel and drain, which is reported for the first time here. The effect of temperature (from 200 K to 500 K) on the GIDL current is also observed, which increases linearly with increasing temperature. Further, the impact of induced mechanical stress (MS) is investigated on the GIDL current, where the GIDL current increases exponentially with increasing induced MS due to effective mass and band gap reduction. Finally, the dynamic performance is investigated in terms of the gate delay time as a function of channel length and temperature. The gate delay diminishes with decreasing channel length and increasing temperature, which shows the switching speed and ability of the device.