Abstract
This paper presents experimental and theoretical analysis of electrical characteristics for recent process‐based low‐temperature polysilicon (LTPS) thin‐film transistors (TFTs) in AMOED displays, focusing on high‐temperature and high‐luminance device characteristics. All off‐state current (Ioff) components in such conditions, which include gate‐induced drain leakage (GIDL), thermal generation, photo generation currents, are in detail analyzed. Exploring the effects of process technologies and device design in small‐size TFTs, in conjunction of reduced defect density‐of‐state (DOS) in the polycrystalline and its interface of gate oxide, we investigate optimal device and process design for reliable polycrystalline thin‐film transistor technologies in high‐brightness and high‐temperature situations. Numerical device simulations, supplemented by physics‐based analysis, confirm experimental results for our optimized device/process and gain diligent process/ design co‐optimization insights.
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