Impact of source/drain lateral straggle on GIDL current of low SS NC-FinFET

Abstract

ABSTRACT In this paper, the gate-induced drain leakage (GIDL) issue in negative capacitance (NC-FinFET) has been comprehensively addressed using Sentaurus 3-D TCAD simulations. Incorporation of ferroelectric (FE) materials in the gate stack of NC-FinFET increases with current by 12% compared to that of baseline FinFET. A steeper sub-threshold swing (SS) of 8 mV/dec is achieved at a FE-thickness of 5 nm at a lateral straggle; (σ) = 0 nm. GIDL behaviour with respect to the variation of source/drain σ and gate oxide thicknesses of NC-FinFET with and without the presence of the GateTunneling model is thoroughly investigated. Investigations demonstrate that in NC-FinFET, there are steeper energy band profiles near source/drain owing to coupling of fringing fields to the ferroelectric layer, which exhibits a larger and prior commencement of the longitudinal band to band tunnelling current compared to conventional FinFET. Moreover, the effect of variation of σ on various parameters viz. SS, capacitance and transconductance has also been investigated, which shows better results for lower σ values. At σ = 0 nm, drain-induced barrier lowering is −187.23 mV/V as compared to that of σ = 5 nm, which is −355.3 mV/V. Furthermore, we have also investigated drain current noise spectral density (SID) and gate voltage noise spectral density (SVG) with respect to fin width (WFIN) at the optimised σ value.