Front Gate Oxide Research Articles

Analytical Modeling and Simulation of a Triple-Material Double-Gate SON TFET with Stacked Front-Gate Oxide for Low-Power Applications

Analytical Modeling and Simulation of a Triple-Material Double-Gate SON TFET with Stacked Front-Gate Oxide for Low-Power Applications

Optimization of a nanoribbon charge-based biosensor using gateless BESOI pMOSFET structure

Nanoribbons built on gateless (GL) Ultra-Thin Body and Buried Oxide (UTBB) Back Enhanced SOI (BESOI) pMOSFET are analyzed as a charge-based (CB) biosensor for different sensing materials and device’s dimensions. Experimental GL UTBB BESOI pMOSFET are used as a reference structure for the CB biosensor and the influence of different materials and the device’s dimensions are studied by numerical simulations. CB biosensor presents higher sensitivities in weak inversion and for negative charges in the front gate oxide once that, for negative charges, the conduction at the front interface in BESOI pMOSFET is favored. An optimization is performed for negative charges and devices with thicker buried oxide (tBOX = 50 nm) and silicon channel (tSi = 20 nm) are more sensitive, improving the BESOI biosensor’s sensitivity in 14% in weak inversion. The improvement in strong inversion is higher (38%) but the absolute value is three times lower. The nanoribbon GL BESOI pMOSFET showed to be a promising structure for an integrated charged based biosensor, which can be easily fabricated in conjunction with the signal processing circuit.

Impact of temperature counting the effect of back gate bias on the performance of extended source tunnel FET (ESTFET) with δp+ SiGe pocket layer

This work presents a comprehensive comparison of temperature affectability on extended source tunnel field effect transistor with δp+ SiGe pocket layer at the tunneling junction with and without the back gate bias. The impacts of temperature on different performance parameters, such as ON and OFF currents, subthreshold swing, threshold voltage, switching ratio, and analog/RF performance of the devices have been investigated. In addition, the effect of Gaussian distribution of trap charges on various interfaces viz. Si–HfO2, Si–SiO2, both Si–HfO2, Si–SiO2 is considered separately. It has been observed that, the effect of temperature on device OFF current is less when trap charges are considered to be present at various interfaces. At low temperature, ESTFET with back gate bias (DG-ESTFET) encounters more variations in performance parameters than without back gate bias ESTFET (SG-ESTFET) considering the presence and absence of trap charges in-between silicon and front gate oxide (Si–HfO2) interface. However, the reverse is found to be true when the trap charges are assumed to be present at the back gate oxide interface (Si–SiO2) and both the interfaces (Si–HfO2, Si–SiO2). Finally, analog/RF performance of ESTFET without back gate bias (SG-ESTFET) is found to be less affected by temperature variations.

Effects of Back-Gate Bias on the Mobility and Reliability of Junction-Less FDSOI Transistors for 3-D Sequential Integration

Low thermal budget junction-less transistors with back-gate are fabricated as top-tier devices for 3-D sequential integration. The impact of back-gate bias on carrier mobility and bias temperature instability (BTI) reliability is investigated. The back-gate bias is shown to modulate the carrier mobility: specifically, mobility is increased under forward back-gate bias (FBB), which is ascribed to the carrier redistribution from the front-gate interface toward back-gate interface. Regarding BTI reliability, if a back-gate bias ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {BG}}{)}$ </tex-math></inline-formula> is applied only during ON-state and a constant front-gate stress <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {G}}$ </tex-math></inline-formula> is used, BTI reliability is not influenced by the applied <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {BG}}$ </tex-math></inline-formula> (due to its negligible impact on the front-gate oxide field, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${E}_{\text {ox}}{)}$ </tex-math></inline-formula> . Therefore, supplying an FBB during ON-state can be used to adjust device performance—as <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {BG}}$ </tex-math></inline-formula> modulates the channel current through <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {th}}$ </tex-math></inline-formula> and mobility—without reliability penalty. On the other hand, if the back-gate bias is applied during both ON- and OFF-states, while a constant stress <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {ov}}$ </tex-math></inline-formula> is maintained by adjusting the front-gate <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {G}}$ </tex-math></inline-formula> [i.e., <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {G}}$ </tex-math></inline-formula> – <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {th}}{(}{V}_{\text {BG}}{)}$ </tex-math></inline-formula> is kept constant under different <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {BG}}$ </tex-math></inline-formula> ’s], the BTI reliability can be improved under FBB (due to a reduced <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${E}_{\text {ox}}$ </tex-math></inline-formula> in the front-gate) without performance loss. The latter property can be used to improve the device reliability under circuit operation.

Comparative Analysis of the Effects of Trap Charges on Single- and Double-Gate Extended-Source Tunnel FET with δp+ SiGe Pocket Layer

This paper investigates the trap analysis of a double-gate extended-source tunnel field-effect transistor (DG-ESTFET) and single-gate extended-source tunnel field-effect transistor (SG-ESTFET) with a δp+ SiGe pocket layer. The trap analysis of both structures is compared in terms of the currents, average subthreshold swing, threshold voltage, and switching ratio. In addition, the impact of interface trap charges at different interfaces on analog/RF performance, transfer characteristics, and slope are investigated and compared. It is observed that the trap charges between the silicon and front gate oxide interface (Si–HfO2) have a greater effect on the DG-ESTFET than the SG-ESTFET, whereas the reverse is true when trap charges are at the back gate oxide interface (Si–SiO2). In the case of analog/RF performance, the SG-ESTFET is found to be more affected by the trap charges at the silicon and front gate oxide interface (Si–HfO2).

Low-Voltage Operating Ferroelectric FET with Ultrathin IGZO Channel for High-Density Memory Application

We have fabricated and demonstrated ultrathin In-Ga-Zn-O (IGZO) channel ferroelectric HfO 2 field effect transistor (FET) with memory operation. Ultrathin-body IGZO ferroelectric FET (FeFET) shows high mobility and nearly ideal subthreshold slop with minimum 8 nm channel thickness, thanks to the properties of IGZO material, junctionless FET operation, nearly-zero low-k interfacial layer on metal-oxide channel and effective capping for realizing ferroelectric phase formation with HfZrO 2 (HZO). The controllable memory operations are achieved with the use of back gate. The design guideline of IGZO FeFET is proposed by discussing the thickness of front gate oxide HZO and back gate oxide SiO 2 using TCAD simulation. The material and electrical properties of metal/HZO/IGZO/metal capacitor are also investigated. Metal/HZO/IGZO/metal capacitor has up to 10 8 endurance and over one-year retention. IGZO FeFET shows a potential for high-density and low-power memory application.

An Analytical Drain Current Model of Gate-On-Source/Channel SOI-TFET

This paper presents an analytical drain current model of Gate-on-Source/Channel SOI-TFET. While deriving the drain current, at first surface potential is derived considering the effect of back gate and considering the effect of bandgap narrowing, energy bands are derived from this surface potential. Finally, the drain current model of Gate-on-Source/Channel SOI-TFET is developed using maximum generation rate of the device. Considering the effect of local minimum present in the energy band diagram of Gate-on-Source/Channel SOI-TFET, maximum generation rate is calculated using a different approach by considering the difference of surface potential between the source region with no gate overlap and the position of local minimum. The proposed model is investigated for front gate voltage, back gate voltage, drain voltage variation. Scalability of the proposed model is analyzed by changing the front gate oxide thickness and body thickness. The model results are compared with the TCAD simulated data to validate the model.

Modeling the threshold voltage variation induced by channel random dopant fluctuation in fully depleted silicon-on-insulator MOSFETs

In nanoscale fully depleted silicon-on-insulator (FD-SOI) MOSFETs, the standard deviation of threshold voltage (σVth) caused by random dopant fluctuation (RDF) is an important parameter to predict the performance of transistors and circuits. In this paper, an analytic model of σVth considering both the dopant “number” and dopant “position” fluctuation in channels is proposed. A new model of σVth,num caused by “number” is given and the method of obtaining the “position” influence ratio Rp is discussed in this paper. Moreover, the simulation methods are analyzed in detail. The calculated σVth values in FD-SOI MOSFETs are compared with the Sentaurus TCAD simulation results at different channel lengths, channel doping concentrations, SOI film thicknesses, front gate oxide thicknesses, and buried-oxide thicknesses. The comparison shows that the proposed model matches well with the obtained numerical simulation results.

A compact interband tunneling current model for Gate-on-Source/Channel SOI-TFETs

A tunneling probability-based drain current model for tunnel field-effect transistors (FETs) is presented. First, an analytical model for the surface potential and the potential at the channel–buried oxide interface is derived for a Gate-on-Source/Channel silicon on insulator (SOI)-tunnel FET (TFET), considering the effect of the back-gate voltage. Next, a drain current model is derived for the same device by using the tunneling probability at the source–channel junction. The proposed model includes physical parameters such as the gate oxide thickness, buried oxide thickness, channel thickness, and front-gate oxide dielectric constant. The proposed model is used to investigate the effects of variation of the front-gate voltage, drain voltage, back-gate voltage, and front-gate dielectric thickness. Moreover, a threshold voltage model is developed and the drain-induced barrier lowering (DIBL) is calculated for the proposed device. The effect of bandgap narrowing is considered in the model. The model is validated by comparison with Technology Computer-Aided Design (TCAD) simulation results.

Exploring the Threshold Voltage Characteristics and Short Channel Behavior of Gate Engineered Front Gate Stack MOSFET with Graded Channel

The present work focuses on formulating a detailed two dimensional analytical model of the proposed Triple Metal Stacked Front Gate Oxide Double Gate MOSFET with step graded channel (GC-TMDG MOSFET) incorporating the dual benefits of gate and channel engineering techniques. Proper choice of a lower work function metal and lower channel doping concentration near the drain end serves the purpose of suppressing the unwanted impact ionization induced Hot Carrier Effects (HCEs) at the drain side of a nano-dimensional device, thereby making it a suitable ultra low dimensional device for future nano generation. The results obtained from analytical modeling depict a detailed comparative analysis of the proposed GC-TMDG MOSFET with its graded channel DG MOSFET counterpart to substantiate the improved performance of the proposed device in terms of surface potential, electric field, threshold voltage roll off, Drain Induced Barrier Lowering and drain current behavior. The analytical results are found to be in good agreement with 2D ATLAS simulator data, thereby validating our analytical model.

New Mobility Model for Accurate Modeling of Transconductance in FDSOI MOSFETs

Anomalous transconductance with nonmono- tonic back-gate bias dependence observed in the fully depleted silicon-on-insulator (FDSOI) MOSFET with thick front-gate oxide is discussed. It is found that the anomalous transconductance is attributed to the domination of the back-channel charge in the total channel charge. This behavior is modeled with a novel two-mobility model, which separates the mobility of the front and back channels. These two mobilities are physically related by a charge-based weighting function. The proposed model is incorporated into BSIM-IMG and is in good agreement with the experimental and simulated data of FDSOI MOSFETs for various front-gate oxides, body thicknesses, and gate lengths.

Low frequency noise behaviors in the partially depleted silicon-on-insulator device

Low frequency noise in the partially depleted silicon-on-insulator (SOI) NMOS device is investigated in this paper. The experimental results show low frequency noise behaviors are in good consistence with classical noise model. Based on McWhorter model, the low frequency noise in the SOI device results from the exchange of carriers between channel and oxide. The densities of trapped charges in the front gate oxide and buried oxide are extracted. Due to the difference between manufacture processes, the extracted density of trapped charges in the buried oxide (Nt=8×1017 eV-1·cm-3) is larger than that in the gate oxide (Nt=2.767×1017 eV-1·cm-3), and the result is in good agreement with testing result of transfer characteristics in part 2. Based on the charge tunneling mechanism, the spatial distribution of trapped charges in the gate oxide and buried oxide are extracted by using the tunneling attenuation coefficient (λ=0.1 nm for SiO2) and time constant (τ0=10-10 s), and the result also proves that the trap in buried oxide is larger than that in gate oxide. In addition, the influence of channel length on the low frequency noise in the SOI device is discussed. The variations of normalized channel current noise power spectral density with channel length are investigated at four frequencies(10 Hz, 25 Hz, 50 Hz, and 100 Hz). The experimental results show that the normalized noise power spectral density decreases linearly with the increase of channel length, which indicates the low frequency noise of SOI device is mainly caused by the flicker noise in the channel, and the contribution of source/drain contact and parasitic resistances could be ignored. Finally, the dependences of back gate voltage on the front gate threshold voltage, front channel current and front channel noise are discussed by considering the charge coupling effect. The experimental results show the measured channel current and channel noise with applying front gate voltage and back gate voltage simultaneously are larger than those with applying the front gate voltage and back gate voltage separately.

Simulations of Transient Behavior and Parasitic Effects for 20 nm Gate Length of PD SOI nMOSFET

In this paper, we report the possible transient behavior for 20nm partially depleted silicon-on-insulator (PD SOI) n-channel MOSFET studied using Synopsys TCAD program. Tunnelling model is set at Si/SiO2 interface by varying front gate oxide. Parasitic floating body effects also have been observed in the device behavior for both linear and saturation regions, the magnitude of these effects depends on the front gate oxide thickness. For 4nm gate oxide thickness, the parasitic floating body effect is dominant at low drain voltage.

Compact Modeling of SOI MOSFETs With Ultrathin Silicon and BOX Layers

The reported compact SOI-MOSFET model hiroshima university starc igfet model-silicon on thin buried oxide (HiSIM-SOTB) has been developed for devices with ultrathin silicon on insulator (SOI) and buried oxide (BOX) layers. The potential distribution determined by the Poisson equation is accurately solved with the Newton iteration method across the SOI layer and in the substrate on the backside of the BOX for source and drain side of the device. All charges including accumulation and inversion charges on both side of the BOX are explicitly considered in the Poisson equation. It is found that different from the double-gate MOSFET, the influence of the impurity concentration of the bulk substrate below the BOX must be also explicitly considered to capture all measured properties of the silicon on thin buried oxide (SOTB) MOSFET. A further modeling challenge of the thin SOI and BOX layers, which had to be overcome, is that charge neutrality is not independently preserved at the front-gate oxide or at BOX side, but only totally within the whole device. Additionally it is found that, due to the consistent potential- and charge-based model formulation, the developed HiSIM-SOTB model can reproduce not only TCAD and measured SOTB device data but is even capable to predict the effects of structural variations, including the limiting case of the double-gate MOSFET structure.

Dual Read Method by Capacitance Coupling Effect for Mode-Disturbance-Free Operation in Channel-Recessed Multifunctional Memory

A channel-recessed multifunctional memory (MFM) device was investigated, and a dual read method using a capacitance coupling effect was developed. The nonvolatile memory (NVM) cells using a SiO2/Si3N4/SiO2 gate insulator and the high-speed single-transistor dynamic random access memory (1T-DRAM) cells using a floating-body effect of an SOI substrate were demonstrated in the single-channel-recessed MFM cells. In order for the layer to avoid the interference of operations between NVM and 1T-DRAM modes, a dual read method using the capacitance coupling effect between a front-gate oxide layer and a back-gate oxide was examined. As a result, a large memory window of NVM operation was accomplished by using the back-gate read operation. Furthermore, the reliability of both NVM and 1T-DRAM operations was improved, and the interferences of operation mode between NVM and 1T-DRAM were effectively suppressed.

Variation Study and Implications for BJT-Based Thin-Body Capacitorless DRAM

Variability in back-gated thin-body capacitorless DRAM cell performance is investigated via TCAD simulation. Sources of variability considered include variations in front gate oxide thickness, body thickness, buried oxide thickness, and gate-sidewall spacer width, as well as random dopant fluctuations. Bipolar junction transistor-based cell operation is most sensitive to variations in body thickness and buried oxide thickness. Retention time for an optimized 22 nm-node cell design is predicted to be reduced by approximately 63% due to process-induced variations.

Investigation of 1/ f noise in germanium-on-insulator 0.12 μm PMOS transistors from weak to strong inversion

This paper presents an experimental analysis of the noise measurements performed in germanium-on-insulator (GeOI) 0.12 μm PMOS transistors from weak to strong inversion. The front gate stack is composed of a HfO2 material with a TiN metal gate (equivalent oxide thickness, EOT, of 1.8 nm). The buried oxide is used as a back gate for experimental purposes. Front gate and back gate oxides/Ge interfaces are characterized. The slow oxide trap densities of the two interfaces are extracted. The values obtained for the front gate oxide are N t ( E Fn) = 1.2 × 10 18 cm −3 eV −1 and are comparable to values for nitrided oxides on Si bulk. The extracted values for slow oxide trap densities of the BOx SiO 2/Ge interface are between 6 and 8 × 10 17 cm −3 eV −1 and are close to those of state of art buried oxide SiO 2/Si interfaces. These results are of importance for the future development of GeOI technologies.

Effect of channel positioning on the 1∕f noise in silicon-on-insulator metal-oxide-semiconductor field-effect transistors

p -channel metal-oxide-semiconductor field-effect transistors (MOSFETs) fabricated on silicon-on-insulator (SOI) substrates with an ultrathin (∼20nm) lightly p-doped Si body were found to show about an order of magnitude lower 1∕f noise than that in conventional bulk Si pMOSFETs when biased in strong inversion. In order to investigate the origin of the 1∕f noise and find an explanation for the 1∕f noise reduction, the 1∕f noise in the SOI devices was studied as a function of the back gate voltage. The 1∕f noise was found to increase with increasing back gate voltage, which acts to push the carriers closer towards the front gate oxide interface. The average distance of the inversion carriers from the gate oxide interface was obtained from simulations and used to interpret the 1∕f noise behavior. The Hooge parameter, extracted for several different 1∕f noise experiments where one or two terminal voltages were varied, exhibited a general behavior similar for both the SOI and bulk Si pMOSFETs. The Hooge parameter was shown to increase markedly when the average carrier-oxide separation is around 2nm. Possible explanations of the results were discussed in terms of the mobility fluctuation noise model.

Electrical stresses on ultra-thin gate oxide SOI MOSFETs after irradiation

We present the first experimental data about the wear-out of a 0.1 /spl mu/m partially depleted SOI CMOS technology after heavy ion irradiation. We show that accelerated life tests based on high electric fields yield significant differences between irradiated and nonirradiated devices, even though no or only minor changes are visible in the characteristics of the devices after irradiation. First, the time to breakdown of the front gate oxide is significantly lower in the irradiated samples. The fresh devices experienced breakdown after 5-8/spl middot/10/sup 22/ electrons/cm/sup 2/ were injected across the oxide during high field electrical stress. In the irradiated oxide, the breakdown was reached at much lower injected charge values, between 0.5/spl middot/10/sup 22/ electrons/cm/sup 2/ and 1.5-1/spl middot/10/sup 22/ electrons/cm/sup 2/ depending on the ion fluences. This translates into a lifetime reduction of 10%-20% of its initial value. Furthermore, the degradation kinetics of the threshold voltage and transconductance peak are strongly affected by ion strikes. In particular, a sudden shift of the threshold voltage and an acceleration in the degradation of the transconductance peak were observed upon the application of an electrical stress, which have no correspondence in nonirradiated devices. An acceleration in the degradation of the parasitic back transistor was observed as well. These phenomena were interpreted in terms of latent damage left by the irradiation in the oxides that make up SOI devices.

SOI technology characterization using SOI-MOS capacitor

In this paper a set of simple methods is presented, to determine the main parameters of the silicon on insulator technology, using a thin film SOI-MOS capacitor. Methods to obtain the effective substrate doping concentration, substrate interface charge density and the buried oxide thickness using the two terminal SOI capacitor are presented. The front gate oxide thickness, the silicon film thickness, the silicon doping concentration and front and back interface charge density are obtained using a three terminal SOI-MOS capacitor. Bidimensional numerical simulations of SOI structure are performed for analyzing the high frequency capacitance vs. voltage curves and to test the proposed methods. These methods were applied experimentally and coherent results were found.