Impact of temperature counting the effect of back gate bias on the performance of extended source tunnel FET (ESTFET) with δp+ SiGe pocket layer

Abstract

This work presents a comprehensive comparison of temperature affectability on extended source tunnel field effect transistor with δp+ SiGe pocket layer at the tunneling junction with and without the back gate bias. The impacts of temperature on different performance parameters, such as ON and OFF currents, subthreshold swing, threshold voltage, switching ratio, and analog/RF performance of the devices have been investigated. In addition, the effect of Gaussian distribution of trap charges on various interfaces viz. Si–HfO2, Si–SiO2, both Si–HfO2, Si–SiO2 is considered separately. It has been observed that, the effect of temperature on device OFF current is less when trap charges are considered to be present at various interfaces. At low temperature, ESTFET with back gate bias (DG-ESTFET) encounters more variations in performance parameters than without back gate bias ESTFET (SG-ESTFET) considering the presence and absence of trap charges in-between silicon and front gate oxide (Si–HfO2) interface. However, the reverse is found to be true when the trap charges are assumed to be present at the back gate oxide interface (Si–SiO2) and both the interfaces (Si–HfO2, Si–SiO2). Finally, analog/RF performance of ESTFET without back gate bias (SG-ESTFET) is found to be less affected by temperature variations.