Ring Oscillator Frequency Research Articles

Gate Stack Analysis of Nanosheet FET for Analog and Digital Circuit Applications

This manuscript demonstrates the performance comparison of vertically stacked nanosheet FET with various high-k materials in gate stack (GS) configuration. As the high-k dielectric materials are inevitable to continual scaling, in this paper, various high-k dielectric materials such as Si3N4, Al2O3 and HfO2 are incorporated in the GS, and the performance is studied. Further, DC and Analog/RF performance metrics are discussed in detail, and it is noticed that by using HfO2 in high-k GS, the on current (I ON) is enhanced by 46.7% and off current (I OFF) is decreased by 81.6% as compared to conventional NSFET (C-NSFET) without high-k GS. Also, the switching ratio (I ON/I OFF) is increased by 8× from SiO2 to HfO2, ensuring good logic applications. Moreover, compared to the C-NSFET, GS-NSFET with HfO2 offers better values for analog metrics like transconductance (gm) and transconductance generation factor (TGF). However, as the k value increases, the capacitances are also observed to be increased. As a result, the intrinsic delay (τ) increases by 9%, 6% and 20% from SiO2 to Si3N4, Si3N4 to Al2O3, Al2O3 to HfO2, respectively. On top of that, the circuit level demonstration is also performed for resistive load based inverter and ring oscillator (RO) for both C-NSFET GS NSFET with HfO2 as GS material. From circuit analysis, it is observed that by using the GS, the performance of the inverter is increased in terms of noise margins and DC gain. However, the oscillation frequency (f OSC) of 3-stage RO is decreased by 14.7% with the incorporation of GS owing to the increment in gate capacitance (Cgg). Consequently, the results will give deep insights into the performance analysis of NSFET with various high-k materials in gate stack at both device and circuit levels.

Exploring the impact of domain numbers on negative capacitance effects in ferroelectric Device-Circuit Co-Design

This paper explores the performance of Hf0.5Zr0.5O2 (HZO)-stacked negative capacitance field-effect transistor (NCFET) for possible beyond complementary metal–oxide–semiconductor (CMOS) technology. For the first time, we investigate the impact of ferroelectric (FE) domain numbers on the negative capacitance (NC) effect, energy dissipation, NC effect voltage window, polarization ramping rate, voltage amplification (ANC), and oscillation frequency of a 5-stage HZO-NCFET inverter-based ring oscillator (HZO-NCFET-RO). The results show that HZO-NCFET is suitable for low-voltage and high-speed applications, providing a significant increase in ANC concerning the conventional PZT-NCFET and P(VDF-TrFE)-NCFET. Our study suggests that the HZO intrinsic NC effect time scale is tiny and limited by the FE switching. We show that the switching time of HZO is ∼20 times faster than the traditional FE [Pb(Nb0.04Zr0.28Ti0.68)O3]. Finally, the proposed 5-stage HZO-NCFET-RO offers superior performance with a 26% higher oscillation frequency and a 94.42% reduction in power dissipation compared to standard 5-stage CMOS inverter-based RO. These findings highlight the potential of HZO-stacked NCFET as an alternative device for the future beyond-CMOS technology.

Prediction of variation aware FOSC in ring oscillators (ROs) to mitigate the impact of aging on RO-PUF

We propose a methodology to predict device-level variability (including aging) impact on the oscillation frequency (Fosc) of an N-stage ring oscillator (RO). This task is accomplished by creating a tool in a Python environment that uses our own developed variability-aware timing models of the CMOS inverter. Moreover, we use the model to foretell the impact of aging on the logical effort (g) of a CMOS inverter. Using the modified g, we resize ROs in an RO-based physical unclonable function (PUF) in the pre-layout stage to mitigate the impact of aging on the reliability of RO-PUF. The simulation is performed in the Cadence AMS environment using STMicroelectronics (STM) 28 nm CMOS process technology. With a one-time SPICE/aging simulation, the proposed methodology eliminates SPICE/aging simulation overhead for the prediction of variability impact on Fosc of a given N-stage RO. This approach mitigates the impact of aging on the reliability of RO-PUF and provides a method for variability (including aging) aware design in the pre-layout stage.

Simulation study of lateral CEFT logic performance at 3 nm Node

In this paper, a lateral CFET comprising of n-type junctionless accumulation mode gate-all-around (JAMGAA) Si-nanowire and p-channel inversion-mode gate-all-around (IMGAA) Si-nanowire FET are proposed. The paper systematically investigates the performance of lateral CFET nanowire for logic applications under three different technology nodes. The performance of the CFET and conventional CMOS is compared and evaluated in terms of voltage transfer characteristics (VTCs), noise margin, voltage gain, transient response, and frequency of a three-stage ring oscillator (RO) using 3D numerical simulation. The results indicate that the n-type JAMGAA has a 6.8% increase in effective driving current compared to the n-type IMGAA, while the effective current is improved by up to 5.5%, due to higher ON-state current of JAMFET. Thanks to such compact structure, the rise time and fall time of the CFET nanowire are improved by up to 21.7% and 25%, respectively, and the frequency of the three-stage RO is improved by up to 4.6% for 3-, 5-, and 7-nm technology nodes. This lateral CFET nanowire improved performance and simplified fabrication, making it a promising candidate in post-moore era.

Improving the accuracy for amplitude and frequency of analytical equation of single-ended ring oscillators based on circuit and transistor parameters

PurposeThis paper aims to find a closed-form expression for the frequency and amplitude of single-ended ring oscillators when transistors experience all regions.Design/methodology/approachIn this paper, the analytical relationships presented for ring oscillator amplitude and frequency are approximately derived due to the nonlinear nature of this oscillator, taking into account the differential equation that governs the ring oscillator and its output waveform.FindingsIn the case where the transistors experience the cut-off region, the relationships presented so far have no connection between the frequency and the dimensions of the transistor, which is not valid in practice. The relationship is presented for the frequency, including the dimensions of the transistor. Also, a simple and approximately accurate relationship for the oscillator amplitude is provided in this case.Originality/valueThe validity of these relationships has been investigated by analyzing and simulating a single-ended oscillator in 0.18 µm technology.

Ultra Low Power Temperature Compensated Complementary Metal Oxide Semiconductor Ring Oscillator in Subthreshold

Low power consumption, low chip area and fabrication in the standard complementary metal oxide semiconductor (CMOS) process are vital requirements for oscillators used in low-cost bio-implantable and wearable devices. Conventional ring oscillators (ROs) are good candidates for using in biomedical applications. However, their oscillation frequency strongly depends on the temperature. In this study, a temperature compensated ring oscillator with low power consumption is proposed. The transistors of the proposed ring oscillator operate in the subthreshold region to achieve a low power and low voltage performance. Since, in the subthreshold region, the oscillation frequency of a conventional ring oscillator increases with increase in the temperature, two current sources are used to power the proposed subthreshold ring oscillator: a temperature independent current source and a complementary to absolute temperature (CTAT) current source. In the proposed circuit, the CTAT current forms a small part of the total supplied current and its duty is to compensate for the oscillation frequency deviation. Two prototypes of the subthreshold ring oscillator were designed and simulated for a target frequency of 1MHz using commercially available 0.18µm RF-CMOS technology. The thermal coefficient (TC) of the uncompensated ring oscillator was 2400 ppm/ºC from -40ºC to 85ºC, though applying the proposed technique reduces the TC of the ring oscillator to 80.4 ppm/ºC with total power consumption as low as 14.5µW.

A Design Strategy to Improve Machine Learning Resiliency for Ring Oscillator Physically Unclonable Function

Physically unclonable functions (PUFs) are hardware security primitives that utilize non-reproducible manufacturing variations to provide device-specific challenge-response pairs (CRPs). Such primitives are desirable for applications such as communication and intellectual property protection. PUFs have been gaining considerable interest from both the academic and industrial communities because of their simplicity and stability. However, many recent studies have exposed PUFs to machine-learning (ML) modeling attacks. To improve the resilience of a system to general ML attacks instead of a specific ML technique, a common solution is to improve the complexity of the system. Structures, such as XOR-PUFs, can significantly increase the nonlinearity of PUFs to provide resilience against ML attacks. However, an increase in complexity often results in an increase in area and/or a decrease in reliability. This study proposes a lightweight ring oscillator (RO)-based PUFs using an additional modulus process to improve ML resiliency. The idea was to increase the complexity of the RO-PUF without significant hardware overhead by applying a modulus process to the outcomes from the RO frequency counter. We also present a thorough investigation of the design space to balance ML resiliency and other performance metrics such as reliability, uniqueness, and uniformity.

Machine Learning-Assisted Device Modeling With Process Variations for Advanced Technology

Process variations (PV), including global variation (GV) and local variation (LV), have become one of the major issues in advanced technologies, which is crucial for circuit performance and yield. However, developing a mature and physics-based model is challenging and time-consuming. Thus, in this work, we propose a machine learning (ML) based method for device modeling with PV and implement the corresponding circuit simulation, which is demonstrated on advanced Nanosheet FETs (NSFET). Verified by TCAD simulations, the artificial neural network (ANN)-based ML algorithm enables to capture PV, e.g., dimension and work function variations (WFV), with high accuracy and improved efficiency. For GV, the ANN surrogated NSFET-based ring oscillator (RO) simulation results show that the larger width (Wsh) or height (Hsh) of the Nanosheet leads to the higher RO frequency and lower circuit delay. For LV, the respective impacts of grain size and WF on circuit performance can be distinguished. The proposed workflow, from ANN model training to circuit simulation based on the generated Verilog-A model, is fully automatic, promising to shorten the procedure of device modeling and accelerate the development of advanced technologies.

Device and circuit-level evaluation of a zero-cost transistor architecture developed via process optimization

In this work, ring oscillator test structures are designed and characterized to evaluate the in-circuit performance of a new medium-voltage (around 2–5 V) transistor architecture developed via process optimization in a 40 nm embedded non-volatile memory (eNVM) CMOS technology. The transistor is zero-cost in terms of photomask and process steps. It is compared to an existing transistor available in the technology. A SPICE model (Simulation Program with Integrated Circuit Emphasis) of the new device is developed to evaluate its circuit-level performance through electrical simulations. The simulation results are complemented by experimental results, and both show a large increase in the ring oscillator frequency for the new transistor, compared to the existing one. In addition, the reliability of the new transistor is evaluated at the device level with hot-carrier injection (HCI) stress tests and at the circuit level with power-supply stress tests.

Stabilizing Techniques for Secure On-chip Key Generation Based on RO-PUF

Based on intrinsic physical characteristics of devices, Physically Unclonable Functions (PUFs) provide the high reliability while maintaining the sufficient uniqueness. However, in the practical implementation based on PUFs, the extracted bit-string normally exhibits the unavoidable small fluctuation. Hence, PUFs can be used for the application of chip identification, but not suitable for the application that strictly requires an exact generated number. In this work, we propose several techniques to stabilize the generated value based on the existing Ring Oscillator (RO)-PUF circuit so that the stable unique number can be directly used for high-profile hardware security applications. In detail, we design a specialized on-chip key generation circuit that repeatedly samples the RO frequency values for statistical analysis and dynamically phases out the unstable bits, resulting in a unique and stable output bit-string. The experiments are conducted for the actual data measured from Xilinx Artix-7 FPGA devices. The generated key is proven to be relatively stable and can be readily used for the emerging security applications.

Total Ionizing Dose Impact on 22-nm FD-SOI Ring Oscillator Current and Frequency

Total ionizing dose (TID) has a significant effect on silicon-on-insulator (SOI) circuits, manifesting primarily as a front-gate threshold voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{t}$ </tex-math></inline-formula> ) shift. This article presents data on ring oscillator (RO) responses of 22-nm fully depleted (FD-SOI) thin oxide (core logic) devices to gamma-ray doses above 1 Mrad(Si). We show large current and frequency TID response differences between ROs comprised of different logic gates. Moreover, the extensive experimental results presented here show that these responses vary significantly with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{t}$ </tex-math></inline-formula> and well type. The measurements show that depending on the expected dose and transistor <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{t}$ </tex-math></inline-formula> used, TID-induced standby current ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$I_{\mathrm {SB}}$ </tex-math></inline-formula> ) increases may have a substantial impact on overall power in spaceborne integrated circuits (ICs) using this fabrication process. The TID impact on digital circuit timing margins is also discussed.

Efficient RO-PUF for Generation of Identifiers and Keys in Resource-Constrained Embedded Systems

The generation of unique identifiers extracted from the physical characteristics of the underlying hardware ensures the protection of electronic devices against counterfeiting and provides security to the data they store and process. This work describes the design of an efficient Physical Unclonable Function (PUF) based on the differences in the frequency of Ring Oscillators (ROs) with identical layout due to variations in the technological processes involved in the manufacture of the integrated circuit. The logic resources available in the Xilinx Series-7 programmable devices are exploited in the design to make it more compact and achieve an optimal bit-per-area rate. On the other hand, the design parameters can also be adjusted to provide a high bit-per-time rate for a particular target device. The PUF has been encapsulated as a configurable Intellectual Property (IP) module, providing it with an AXI4-Lite interface to ease its incorporation into embedded systems in combination with soft- or hard-core implementations of general-purpose processors. The capability of the proposed RO-PUF to generate implementation-dependent identifiers has been extensively tested, using a series of metrics to evaluate its reliability and robustness for different configuration options. Finally, in order to demonstrate its utility to improve system security, the identifiers provided by RO-PUFs implemented on different devices have been used in a Helper Data Algorithm (HDA) to obfuscate and retrieve a secret key.

Remaining useful life (RUL) regression using Long–Short Term Memory (LSTM) networks

The accurate prediction of the remaining useful life (RUL) of components is a major concern in electronic circuits. The RUL-based health diagnostics plays an important role in the determination of time-of-failure of a device as an early warning in industrial applications. In this paper, a Long Short Term Memory (LSTM) based regression model is proposed for the prediction of RUL of a Ring Oscillator (RO) circuit utilizing the most essential extracted electrical features of the device. LSTM networks are capable of capturing the temporal dependencies in the time-series data and eliminating the vanishing gradient problem encountered in the conventional recurrent neural networks (RNNs). From Cadence simulations, utilizing the 22 nm CMOS technology library, it has been demonstrated that the RO frequency degradation essentially depends on three major factors including the working temperature, voltage, and most importantly, the device aging parameter. The results show that more than 90% of the cases of the RUL prediction for the 13 and 21 stage constrained under the supply voltage variation from 0.7 V to 0.9 V with the least prediction deviation of 2 days to 6 days.

A Novel Bias Circuit Technique to Reduce the PVT Variation of the Ring Oscillator Frequency

Phase Locked Loop (PLL) is an on-chip clock generator for timing-centric electronic systems. Voltage Controlled Oscillator (VCO) is the key element for high-performance PLLs. A detailed qualitative explanation has been given to describe VCO operation. It is shown from simulation results that the variation of small signal transconductance ([Formula: see text]) is the main dominant source of frequency and gain ([Formula: see text]) variation in a VCO. In this work, simulation results for the conventional ring oscillator are presented which demonstrates [Formula: see text] times variation in [Formula: see text] across Process Voltage Temperature (PVT) corners. Such huge sensitivity to PVT is undesirable for high bandwidth PLL design. To mitigate this sensitivity, a constant-gm bias circuit is proposed in this paper, with a detailed mathematical analysis. A prototype of 4-stage ring oscillator with center frequency of 5[Formula: see text]GHz is developed in 65[Formula: see text]nm TSMC CMOS technology, and post-layout simulation results are carried out. Results show that maximum [Formula: see text] variation of 28% and frequency variation of 17% at a given control voltage. Temperature sensitivity has been decreased from 19.3% to 7% using the proposed biasing technique. Proposed solution consumes 2.4[Formula: see text]mW power from 1[Formula: see text]V power supply.

Development of a high accuracy and stability test bench for ageing measurement of 16 nm FinFETs based FPGA

This article describes the development of a test bench so as to measure the ageing of 16 nm FinFETs used in a Zynq UltraScale+ FPGA from Xilinx. The Ring Oscillator (RO) drift measurement method was chosen and implemented in the setup. However, RO is a circuit sensitive not only to ageing but also to temperature and voltage. In order to mitigate the undesired sensitivity to temperature and voltage, we installed a regulation system to control the temperature and the internal voltage of the FPGA, and we characterised the RO frequency in function of the temperature and the voltage to apply post-measurement compensations. We improved the measurement circuit by using the GPS signal as a time reference. 1000 h test with (TFPGA = 100∘C) and (VFPGA = Vnom + 25%) was performed and results show clear RO frequency drifts lower than 0.1 % measured with an accuracy of 0.9 × 10−4.

Performance investigation of Ge DLTFET based digital integrated circuit

ABSTRACT The article investigates the performance of germanium source doping-less tunnel FET (Ge DLTFET)-based digital integrated circuits. For this, the compact models have been developed for DLTFETs using Verilog-A approach. Furthermore, at circuit level, the performance of Ge DLTFET is compared with its conventional counterpart silicon source DLTFET (Si DLTEFT). Two digital benchmark circuits are considered for circuit simulation such as ring oscillator (RO) and conventional six-transistor static random-access memory (6 T SRAM). The simulation results depict that the operating frequency of Ge DLTFET RO is ~ 4.48 decade higher than Si DLTFET. Similarly, the performance of Ge DLTFET SRAM cell in terms of read and write delay is much better than its conventional counterpart Si DLTFET. Hence, Ge DLTFET can be considered as a promising device structure for high-speed digital circuit design and for its applications.

Systematic Unsupervised Recycled Field-Programmable Gate Array Detection

With the expansion of the semiconductor supply chain, the use of recycled field-programmable gate arrays (FPGAs) has become a serious concern. Several methods for detecting recycled FPGAs by analyzing the ring oscillator (RO) frequencies have been proposed; however, most assume the known fresh FPGAs (KFFs) as the training data in machine-learning-based classification. In this study, we propose a novel recycled FPGA detection method based on an unsupervised anomaly detection scheme when there are few or no KFFs available. As the RO frequencies in the neighboring logic blocks on an FPGA are similar because of systematic process variation, our method compares the RO frequencies and does not require KFFs. The proposed method efficiently identifies recycled FPGAs through outlier detection using direct density ratio estimation. Experiments using Xilinx Artix-7 FPGAs demonstrate that the proposed method successfully distinguishes recycled FPGAs from 35 fresh FPGAs. In contrast, a conventional recycled FPGA detection method results in certain misclassification.

Comprehensive Analytical Comparison of Ring Oscillators in FDSOI Technology: Current Starving Versus Back-Bias Control

Back-bias control is a new degree of freedom brought by fully-depleted silicon-on-insulator (FDSOI) CMOS technologies, which can be used to control the oscillation frequency of voltage-controlled ring oscillators (VCROs). The resulting VCRO architecture is called a back-bias-controlled oscillator (BBCO). This paper compares it with the conventional current-starved ring oscillator (CSRO) topology in terms of power consumption and phase noise figure-of-merit (FoM), while taking practical design constraints of process-voltage-temperature (PVT) robustness and frequency tuning range into account. The proposed comprehensive analysis takes advantage of relevant and compact analytical models, as well as extensive pre-layout simulation results. The comparison is made at four different target oscillation frequencies, which are representative of frequency synthesis for WiFi/Bluetooth/LPWAN wireless communications and of clock generation for smartphone/Internet-of-Things processors: 300 MHz, 868 MHz, 2.45 GHz, and 5.18 GHz. In 28-nm FDSOI technology, the results demonstrate that BBCOs can intrinsically reach 1.69 to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4.63\times $ </tex-math></inline-formula> lower minimum power consumption and slightly better FoM values than CSROs.

Effect of Frequency on Total Ionizing Dose Response of Ring Oscillator Circuits at the 7-nm Bulk FinFET Node

Total ionizing dose (TID) effects at the 7-nm bulk FinFET node are characterized under dynamic and static test conditions through changes in ring oscillator (RO) frequencies, leakage currents, and inverter delays. Results from total-dose exposures using the ARACOR X-ray machine showed that static conditions represented the worst case conditions. Higher operating frequencies resulted in increased leakage currents and inverter delays after irradiation. The rate of change for leakage current was inversely proportional to frequency during exposure. The rate of change for inverter delay was directly related to frequency during TID exposure. Overall, degradations in circuit-level parameters (logic gate delays and operating current) were less than 1% for TID exposures of 435 krad(SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ).

Performance Analysis of Tunnel FET Based Ring Oscillator Using Sentaurus TCAD

A detailed Sentaurus TCAD simulation based study for Silicon Double Gate Tunnel Field Effect Transistor (Si-DG TFET) based Ring Oscillator (RO) is presented in this work. Two different ring oscillator topologies (simple RO and Negative Skewed Delay RO )are presented with two different structures for TFET device. The two structures are different in the source-drain extension regions widths. The extension region width variation effects are studied and presented for inverter and ring oscillator. A TFET based inverter is presented to show the changes in behavior due to variations in the drain extension region widths, which is later used for RO designs. The drain extension region width changes the drain extension region resistances which in turn is responsible for change in the corresponding device properties. RO simulation are used for calculating the delay. To further explore digital and analog applications transfer characteristics and noise margins of inverter are explored with power supplies variations. Better reliability for oscillation frequency is obtained using Negative Skewed Delay ring oscillator (NSD RO) topology. NSD RO is resulting in lesser jitter, more reliable frequency as compared to single-ended ring oscillator topology. By tuning the supply voltage of the device the ring oscillator frequency can be used for RF applications, thus it works like a voltage controlled oscillator (VCO).