Simulation study of lateral CEFT logic performance at 3 nm Node

Abstract

In this paper, a lateral CFET comprising of n-type junctionless accumulation mode gate-all-around (JAMGAA) Si-nanowire and p-channel inversion-mode gate-all-around (IMGAA) Si-nanowire FET are proposed. The paper systematically investigates the performance of lateral CFET nanowire for logic applications under three different technology nodes. The performance of the CFET and conventional CMOS is compared and evaluated in terms of voltage transfer characteristics (VTCs), noise margin, voltage gain, transient response, and frequency of a three-stage ring oscillator (RO) using 3D numerical simulation. The results indicate that the n-type JAMGAA has a 6.8% increase in effective driving current compared to the n-type IMGAA, while the effective current is improved by up to 5.5%, due to higher ON-state current of JAMFET. Thanks to such compact structure, the rise time and fall time of the CFET nanowire are improved by up to 21.7% and 25%, respectively, and the frequency of the three-stage RO is improved by up to 4.6% for 3-, 5-, and 7-nm technology nodes. This lateral CFET nanowire improved performance and simplified fabrication, making it a promising candidate in post-moore era.