Ring Oscillator Frequency Research Articles

Improved ring oscillator PUF on FPGA and its properties

PUFs (Physical Unclonable Function) are increasingly used in proposals of security architectures for device identification and cryptographic key generation. Many PUF designs for FPGAs proposed up to this day are based on ring oscillators (RO). The classical approach is to compare frequencies of ROs and produce a single output bit from each pair of ROs based on the result of comparison of their frequencies. This ROPUF design requires all ROs to be mutually symmetric and also the number of pairs of ROs is limited in order to preserve the independence of bits in the PUF response. This led us to design a new ROPUF on FPGA which is capable of generating multiple output bits from each pair of ROs and is also allowing to create higher number of pairs of ROs, thereby making the use of ROs more efficient than the classical approach. Our PUF design is based on selecting a particular part of a counter value and using it for the PUF output. By applying Gray code on the counter values, we have considerably improved the PUF’s statistical properties. In principle, this PUF design does not need the ROs to be mutually symmetric, however, it is shown that this ROPUF design has significantly better properties with varying supply voltage when symmetric ROs are used. All of the presented measurements were performed on Digilent Basys 2 FPGA Boards (Xilinx Spartan3E-100 CP132). In this work, we provide a more detailed description of the PUF design on FPGA and the behaviour of ROs with varying supply voltage. Our proposed PUF architecture offers more output bits with required statistical properties from each RO pair than the classical approach, where frequencies of ROs are compared. The presented improvements significantly reduce the dependence on fluctuation of supply voltage.

The Oscillation Frequency of CML-based Multipath Ring Oscillators

A novel phase interpolator (PI) based linear model of multipath ring oscillator (MPRO) is described in this paper. By modeling each delay cell as an ideal summer followed by a single pole RC filter, the oscillation frequency is derived for a 4-stage differential MPRO. It is analytically proved that the oscillation frequency increases with the growth of the forwarding factor α, which is also confirmed quantitatively through simulation. Based on the proposed model, it is shown that the power to frequency ratio keeps constant as the speed increases. Running at the same speed, a 4-stage MPRO can outperform the corresponding single-stage ring oscillator (SPRO) with 27% power saving, making MPRO with a large forwarding factor α an attractive option for lower power applications.

Modeling Static Delay Variations in Push–Pull CMOS Digital Logic Circuits Due to Electrical Disturbances in the Power Supply

Soft errors can occur in digital integrated circuits (ICs) as a result of an electromagnetic disturbance, such as might result from an electrical fast transient (EFT). Many soft errors come from changes in propagation delays through digital logic, which are caused by changes in the on-die power supply voltage. An analytical model was developed to predict timing variations in digital logic as a result of variations in the power supply voltage. The derivation of the analytical delay model is reported. The model was validated experimentally by applying EFTs to a ring oscillator built in a test IC. The predicted and measured ring oscillator frequencies (or periods) agreed within a relative error of less than 2.0%. To further validate the approach, the model was applied to test the response of more complex circuits consisting of NAND/NOR logic gates, binary adders, dynamic logic gates, and transmission gates. The circuits were fabricated on a 0.5 μm test IC and simulated on two additional process technologies (0.18 μm and 45 nm). The model performed well in each case with a maximum relative error of 5.6%, verifying the applicability of the model for analyzing complex logic circuits within a variety of process technologies. The proposed delay model can be used by IC design engineers to predict and understand the change in the propagation delay through logic circuits due to the disturbed power supply.

Impacts of Trapezoidal Fin of 20-nm Double-Gate FinFET on the Electrical Characteristics of Circuits

In this study, we analyze the impacts of the trapezoidal fin shape of a double-gate FinFET on the electrical characteristics of circuits. The trapezoidal nature of a fin body is generated by varying the angle of the sidewall of the FinFET. A technology computeraided-design (TCAD) simulation shows that the onstate current increases, and the capacitance becomes larger, as the bottom fin width increases. Several circuit performance metrics for both digital and analog circuits, such as the fan-out 4 (FO4) delay, ring oscillator (RO) frequency, and cut-off frequency, are evaluated with mixed-mode simulations using the 3D TCAD tool. The trapezoidal nature of the FinFET results in different effects on the driving current and gate capacitance. As a result, the propagation delay of an inverter decreases as the angle increases because of the higher on-current, and the FO4 speed and RO frequency increase as the angle increases but decrease for wider angles because of the higher impact on the capacitance rather than the driving strength. Finally, the simulation reveals that the trapezoidal angle range from 10° to 20° is a good tradeoff between larger on-current and higher capacitance for an optimum trapezoidal FinFET shape.

링발진기를 이용한 CMOS 온도센서 설계

The temperature sensor using ring oscillator is designed by 0.18㎛ CMOS process and the supply voltage is 1.5volts. The temperature sensor is designed by using temperature-independent and temperature-dependent ring oscillators and the output frequency of temperature-independent ring oscillator is constant with temperature and the output frequency of temperature-dependent ring oscillator decreases with increasing temperature. To convert the temperature to a digital value the output signal of temperature-independent ring oscillator is used for the clock signal and the output signal of temperature-dependent ring oscillator is used for the enable signal of counter. From HSPICE simulation results, the temperature error is less than form -0.7℃ to 1.0℃ when the operating temperature is varied from -20℃ to 70℃.

Analysis of frequency and amplitude in CMOS differential ring oscillators

In this paper, a new method for computing the amplitude and frequency of differential ring oscillators (ROs) is proposed. The analysis is performed in two separate parts. In the first of these, equations are derived with the assumption of a sinusoidal waveform of outputs, while in the other, the outputs are assumed to be exponential. It is shown that the derived equations for frequency and amplitude are sufficiently exact. In addition, conditions in which sinusoidal and exponential output occur are thoroughly discussed. In the instances in which the results did not satisfy the necessary conditions for sinusoidal output, the output is assumed to be exponential. Moreover, the related analytical equations are written, and the new expressions for frequency and amplitude of ROs are derived. Analytical results are confirmed by simulation results, using the Taiwan Semiconductor Manufacturing Company 0.18µm technology model. The simulation results indicate the high level of accuracy of the proposed model.

4H-SiC JFET Multilayer Integrated Circuit Technologies Tested up to 1000 K

Testing of semiconductor electronics at temperatures above their designed operating envelope is recognized as vital to qualification and lifetime prediction of circuits prior to deployment in beneficial applications. This work describes the high temperature electrical testing of prototype 4H silicon carbide (SiC) junction field effect transistor (JFET) integrated circuit technology implemented with multilayer interconnects intended for prolonged operation in applications at temperatures up to 773K (500 °C). A 50mm diameter sapphire wafer was used in place of the standard NASA packaging for this experiment. Testing was carried out between 300K (27 °C) and 1150K (877 °C) with successful electrical operation of all devices observed up to 1000K (727 °C). We tested each of the following devices: Transmission Line Method (TLM) test structure, discrete JFET with a gate length of 6 µm and width of 12 µm, discrete on-chip capacitor of area about 0.5mm2, 3-stage ring oscillator comprising of 12 JFET transistors and 30 resistors, and one open-circuit trace on the sapphire wafer to test leakage of everything up to the die. These devices resided on a single 3mm x 3mm SiC die that was bonded via die-attach paste to a 50mm sapphire wafer “package” with patterned 1µm thick gold traces. The lateral spacing of gold traces on sapphire was 3.175mm. The die attach paste is conductive, providing backside electrical contact necessary for stable device operation. 25µm diameter gold ball/wedge bonds connected chip pads to gold traces on the sapphire wafer, and 250 µm diameter gold wires with glass fiber insulation connected the sapphire wafer to a terminal strip outside an oven. The die remained uncovered for the duration of the test. The thermal profile started with a ramp at 3K/minute from 300K to 773K. Then the sample remained at 773K for 22 hours. The 22-hour “burn-in” at 773K was performed because significant reductions in leakage have been observed during previous testing at this temperature. The final ramp from 773K to 1150K was at 9K/minute. The JFET and TLM were measured with a digitizing curve tracer, while the capacitor and sapphire wafer leakages were measured with source-measure units. Ring oscillator output was measured with a 10M-Ohm probe AC-coupled to digitizing oscilloscope. The devices were continuously biased, but only measured every 90 seconds during the thermal ramps and every 2 hours during the 773K “burn in.” The 3-stage ring oscillator frequency decreased from ~850 kHz at 773K to ~660 kHz at 1000K with output amplitude that decreased from 130mV to 20 mV. The JFET exhibited saturation current of 280 µA at 300K that decreased to 50 µA at 1000K. The n-type TLM exhibited specific contact resistance of less than 4 x 10-4 µÙ cm2 throughout the test, and a sheet resistance of 5 kµÙ/square at 300K that increased to 38 kµÙ/square at 1000K with approximately T2power law behavior. No leakage above open-circuit noise floor was observed from the capacitor at 20V bias until 600K. The leakage increased with temperature until 686K at 378 µA at which point the 20V leakage began to drop even while the temperature was increasing. By the time the capacitor had reached the start of the 773K burn in period the leakage had dropped to ~100 µA. The capacitor had measurable leakage again when heated to above 990K and then the max leakage remained below 100 µA. The sapphire did not have measurable 20V leakage until 850K, which increased to 68 nA at 1000K. Above 1000K all devices started to demonstrate behavior consistent with loss of the backside bias connection. Upon cooling and inspection it was found that the backside contact metal on the die and the gold trace area on the sapphire became transparent where there was die attach paste. There were cracks in the on-chip SiO2dielectric formed from low pressure chemical deposition (LPCVD) using tetraethyl orthosilicate (TEOS) precursor at the corners of some metal traces. Some of the gold ball bonds wires had melted. The peak oven temperature reached 1150K before the oven was turned off so a clear sequence of causality is hard to determine; therefore, electrical data reported is only to 1000K corresponding to apparent loss of backside bias.

A Low-Power Hybrid RO PUF With Improved Thermal Stability for Lightweight Applications

Ring oscillator (RO)-based physical unclonable function (PUF) is resilient against noise impacts, but its response is susceptible to temperature variations. This paper presents a low-power and small footprint hybrid RO PUF with a very high temperature stability, which makes it an ideal candidate for lightweight applications. The negative temperature coefficient of the low-power subthreshold operation of current starved inverters is exploited to mitigate the variations of differential RO frequencies with temperature. The new architecture uses conspicuously simplified circuitries to generate and compare a large number of pairs of RO frequencies. The proposed nine-stage hybrid RO PUF was fabricated using global foundry 65-nm CMOS technology. The PUF occupies only 250 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> of chip area and consumes only 32.3 μW per challenge response pair at 1.2 V and 230 MHz. The measured average and worst-case reliability of its responses are 99.84% and 97.28%, respectively, over a wide range of temperature from -40 to 120 °C.

Fast Wafer-Level Stress-and-Sense Methodology for Characterization of Ring-Oscillator Degradation in Advanced CMOS Technologies

Ring oscillators (ROs) are widely used to study the degradation of logic CMOS circuits. To successfully link the time dependence of the ROs frequency degradation to the degradation of discrete device, we introduce a novel, fast wafer-level stress-and-sense methodology. With this new methodology, we unambiguously show the close correlation between discrete device degradation and circuit aging at typical wafer-level stress times.

Initial and long-term frequency degradation of ring oscillators caused by plasma-induced damage in 65 nm bulk and fully depleted silicon-on-insulator processes

The degradation of reliability caused by plasma-induced damage (PID) has become a significant concern with the miniaturization of device size. In particular, it is difficult to relieve PID in silicon-on-insulator (SOI) because it contains buried oxide (BOX) layers. In this work, we compare PID between a bulk and a silicon on thin BOX (SOTB), which has BOX layers of less than 10 nm. We measure frequencies of ring oscillators with an antenna structure on a single stage. In the bulk, PID is relieved by first connecting an antenna to a drain because electric charge flows to a substrate. The difference in initial frequency is 0.79% between structures, which cause and relieve PID. SOTB also relieves the same amount of PID. Initial frequencies are affected by PID, but there is no effect of PID on the long-term degradation mainly caused by bias temperature instability (BTI).

Scaling of pneumatic digital logic circuits.

The scaling of integrated circuits to smaller dimensions is critical for achieving increased system complexity and speed. Digital logic circuits composed of pneumatic microfluidic components have to this point been limited to a circuit density of 2-4 gates cm(-2), constraining the complexity of the digital systems that can be achieved. We explored the use of precision machining techniques to reduce the size of pneumatic valves and resistors, and to achieve more accurate and efficient placement of ports and vias. In this way, we attained an order of magnitude increase in circuit density, reaching as high as 36 gates cm(-2). A 12-bit binary counter circuit composed of 96 gates was realized in an area of 360 mm(2). The reduction in size also brought an order of magnitude increase in speed. The frequency of a 13-stage ring oscillator increased from 2.6 Hz to 22.1 Hz, and the maximum clock frequency of a binary counter increased from 1/3 Hz to 6 Hz.

Flexible logic circuits based on top-gate thin film transistors with printed semiconductor carbon nanotubes and top electrodes.

In this report printed thin film transistors and logic circuits on flexible substrates are reported. The top-gate thin film transistors were made of the sorted semiconducting single-walled carbon nanotubes (sc-SWCNTs) ink as channel material and printed silver lines as top electrodes and interconnect. 5 nm HfOx thin films pre-deposited on PET substrates by atomic layer deposition (ALD) act as the adhesion layers to significantly improve the immobilization efficiency of sc-SWCNTs and environmental stability. The immobilization mechanism was investigated in detail. The flexible partially-printed top-gate SWCNT TFTs display ambipolar characteristics with slightly strong p-type when using 50 nm HfO(x) thin films as dielectric layer, as well as the encapsulation layer by atomic layer deposition (ALD) at 120 °C. The hole mobility, on/off ratio and subthreshold swing (SS) are ∼ 46.2 cm(2) V(-1) s(-1), 10(5) and 109 mV per decade, respectively. Furthermore, partially-printed TFTs show small hysteresis, low operating voltage (2 V) and high stability in air. Flexible partially-printed inverters show good performance with voltage gain up to 33 with 1.25 V supply voltage, and can work at 10 kHz. The frequency of flexible partially-printed five-stage ring oscillators can reach 1.7 kHz at supply voltages of 2 V with per stage delay times of 58.8 μs. This work paves a way to achieve printed SWCNT advanced logic circuits and systems on flexible substrates.

A high-yield vacuum-evaporation-based R2R-compatible fabrication route for organic electronic circuits

Advances are described in a vacuum-evaporation-based approach for the roll-to-roll (R2R) production of organic thin film transistors (TFTs) and circuits. Results from 90-transistor arrays formed directly onto a plasma-polymerised diacrylate gate dielectric are compared with those formed on polystyrene-buffered diacrylate. The latter approach resulted in stable, reproducible transistors with yields in excess of 90%. The resulting TFTs had low turn-on voltage, on–off ratios ∼106 and mobility ∼1cm2/Vs in the linear regime, as expected for dinaphtho[2,3-b:2′,3′-f] thieno[3,2-b]thiophene the air stable small molecule used as the active semiconductor. We show that when device design is constrained by the generally poor registration ability of R2R processes, parasitic source–drain currents can lead to a >50% increase in the mobility extracted from the resulting TFTs, the increases being especially marked in low channel width devices. Batches of 27 saturated-load inverters were fabricated with 100% yield and their behaviour successfully reproduced using TFT parameters extracted with Silvaco’s UOTFT Model. 5- and 7-stage ring oscillator (RO) outputs ranged from ∼120Hz to >2kHz with rail voltages, VDD, increasing from −15V to −90V. From simulations an order of magnitude increase in frequency could be expected by reducing parasitic gate capacitances. During 8h of continuous operation at VDD=−60V, the frequency of a 7-stage RO remained almost constant at ∼1.4kHz albeit that the output signal amplitude decreased from ∼22V to ∼10V. Over the next 30days of intermittent operation further degradation in performance occurred although an unused RO showed no deterioration over the same period.

Correlations between BTI-Induced Degradations and Process Variations on ASICs and FPGAs

We analyze the correlation between BTI (Bias Temperature Instability) -induced degradations and process variations. Those reliability issues are correlated. BTI is one of the most significant agingdegradations on LSIs. Threshold voltages of MOSFETs increase with time when biases stress their gates. It shows a strong effect of BTI on highly scaled LSIs in the same way as the process variations. The accurate prediction of the combinational effects is indispensable. We should analyze both aging-degradations and process variations of MOSFETs to explain the correlation. We measure frequencies of ROs (Ring Oscillators) of 65-nm process test circuits on two types of LSIs, ASICs and FPGAs. There are 98 and 837 ROs on our ASICs and FPGAs respectively. The frequencies of ROs follow gaussian distributions. We describe the highest frequency group as the “fast” conditon, the average group as the “typical” conditon and the lowest group as the “slow” conditon. We measure the aging-degradations of the ROs of the three conditions on the accelerated test. The degradations can be approximated by logarithmic function of stress time. The degradation at the “fast” condition has a higher impact on the frequency than the “slow” one. The correlation coefficient is 0.338. In this case, we can define a smaller design margin for BTI-induced degradations than that without considering the correlation because the degradation at the “slow” conditon is smaller than the average and the fast. key words: BTI, process variation, reliability

Simulation of TID Effects in a High Voltage Ring Oscillator

Oscillation frequency of a high voltage ring oscillator is observed to change non-linearly with increasing dose. The change in oscillation is caused by buildup of oxide-trapped charge in both gate and isolation oxides post-radiation. A simulation methodology is described and implemented which successfully re-creates oscillator response by way of radiation-enabled simulation. Implementation of radiation-enabled simulation of ring oscillator is discussed. Simulation allows projection of oscillator response in-situ, allowing designers to anticipate changes in oscillation and implement radiation hardening as required. Alternatively, implementation of a ring oscillator as a reliability monitor in a large-scale circuit allows easily detectable observation of total dose effects on transistors.

Low Voltage and High Oscillation Frequency Gated Ring Oscillator Using Bootstrap Technique

In this paper, a high frequency ring oscillator with low power consumption is proposed.The proposed ring oscillator is based on GRO by applying boot strap technique. Simulation resultsindicate that the FoM(Power Consumption/Oscillation Frequency) of the proposed ring oscillator isless than that of the conventional ring oscillator.

Out-of-plane MEMS-based mechanical airflow sensor co-integrated in SOI CMOS technology

This paper demonstrates the monolithic integration of an airflow sensor based on out-of-plane movable cantilevers with a CMOS integrated circuit providing small footprint and low-power sensing. Airflow is sensed by mechanical deflection of cantilevers without static power consumption contrary to classical thermal flow sensors based on micro-heater. The interfacing circuit is a CMOS ring oscillator (RO), fabricated on the same chip with silicon-on-insulator (SOI) technology, offering unique properties such as harsh environment resistance and lower power consumption. Moreover, the additional post-processing steps required by the built-in of out-of-plane cantilevers are minimum thanks to the use of standard CMOS materials and dry etching of the sacrificial layer.The developed microsystem demonstrates 10% variation of the RO frequency for an airflow varying from 0m/s to 120m/s, with a static power consumption of the order of 1μW.

Inhomogeneous Ring Oscillator for Within-Die Variability and RTN Characterization

This paper discusses the concept of an inhomogeneous structure for a ring oscillator (RO) to enhance the delay effect of a particular inverter stage. The frequency of the proposed inhomogeneous structure becomes a strong function of the inhomogeneous stage; thus, the variability becomes directly visible. With careful design of the inhomogeneous stage, the RO frequency can be made sensitive to a small set of transistors for characterizing transistor-by-transistor variability. Performance sensitivities of the transistors are enhanced more than 100 times that of other transistors in the RO. The proposed ROs are embedded into a 65-nm RO-array test structure, and it is verified that these ROs are highly sensitive to within-die local variability and random telegraph noise (RTN). The within-die local variability is then successfully decomposed into threshold voltage and gate length variations. Several characteristics of RTN have been successfully extracted with the proposed structure. The proposed structure is thus very useful for observation, characterization and modeling of static and dynamic transistor variations during switching operation.

A Ring Oscillator With Calibration Circuit for On-Chip Measurement of Static IR-drop

Resource estimation of a power distribution network (PDN) is a critical issue for the resource management of LSIs. To evaluate the impact of PDN parameters to the quality of power delivery, an accurate PDN simulation model is necessary. To reflect the real silicon's behavior to PDN simulation models, we propose a test structure that consists of an array of Ring Oscillators (ROs) with calibration circuits for static IR-drop measurement. The calibration circuit is used for the estimation of the RO frequency without any IR-drops so that we can estimate the absolute value of the IR-drop under circuit operation. A test chip which includes 540 ROs and 270 calibration circuits is fabricated in a 65 nm process. The maximum discrepancy between the measurement and simulation values is 0.18% in standby mode, and 0.76% for additional current loading mode.

High-Speed 501-Stage DCFL GaN Ring Oscillator Circuits

Direct-coupled field-effect transistor (FET) logic inverters and 501-stage ring oscillators (ROs) are fabricated using highly scaled GaN heterojunction FET with gate lengths of 20 and 40 nm. A 40-nm gate-length E/D inverter has logic-low and logic-high noise margins of 0.465 and 1.59 V, respectively, and a logic voltage swing of 2.38 V measured at Vdd = 2.5 V. The corresponding 40-nm 501-stage RO frequency and stage delay are 0.067 GHz and 15 ps, whereas the frequency and stage delay of a 20-nm RO are 0.133 GHz and 7.5 ps. The yield of the 20-nm 501-stage RO circuits is 52% across a 3-in diameter wafer. With 1006 transistors, the 501-stage ROs represent the highest level of transistor integration to date for a GaN circuit, whereas the stage delay is the shortest reported for a GaN digital circuit.