Ring Oscillator Frequency Research Articles

Differential Aging Sensor Using Subthreshold Leakage Current to Detect Recycled ICs

Electronic system components can fall prey to counterfeiting via untrustworthy parties in the semiconductor supply chain, which has established a worldwide span to reduce costs, time to market, and increase productivity. Recently, integrated circuits (ICs) counterfeiting has threatened systems security and reliability that utilize ICs in all domains. This article focuses on the most counterfeited area—recycled and remarked ICs—and aims to develop a technique to distinguish between new and used digital ICs based on an aging sensor mechanism. Aging sensors have been studied based on path-delay fingerprinting and ring oscillators (ROs) frequency degradation, but their resolution requires further development to accurately detect short usage. This study proposes a novel differential aging sensor to measure the discharge time ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\tau {{{dv}}}$ </tex-math></inline-formula> ) increase that depends on the subthreshold leakage current due to aging with two on-chip designs. Simulations were conducted using the GlobalFoundries (GF) 22 nm for aging with bias temperature instability and hot carrier injection (HCI) combined. The results show that the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\tau {{{dv}}}$ </tex-math></inline-formula> increase is 14.72% after 15 days of usage and increases to 60.49% after three years. This further increases at higher temperatures; the highest simulated temperature ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$125~^{\circ }\text{C}$ </tex-math></inline-formula> ) <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\tau {{{dv}}}$ </tex-math></inline-formula> increases by 55.93% after 15 days and 310.17% after three years. The proposed method also outperformed the traditional frequency degradation-based aging estimation method, which at nominal temperature is found to be 5.00% after 15 days and 23.68% after three years. Therefore, discharge time is a sensitive indicator for aging, surpasses frequency in detecting previous usage and is robust against process, voltage, and temperature variations (PVTs).

Three counter value based ROPUFs on FPGA and their properties

This paper investigates the behavior of the Physical Unclonable Function (PUF) design proposed in our previous work that is based ring oscillators (ROs). Our approach is able to extract multiple output bits from each RO pair in contrary to the classical approach, where frequencies of ROs are compared. We study the behavior of our PUF design together with other two similar proposals that are also based on extracting PUF bits from counter values.In this work we compare the behavior of three PUF designs that are based on extracting PUF bits from counter values with one of them being proposed in our previous work. We evaluate these proposals at both stable and varying temperature and voltage in order to determine their robustness. The results show that our proposed technique, the frequency ratio, is the most reliable one. Furthermore, we compare the behavior of all of the three designs when mutually asymmetric and symmetric ROs are used. All of the measurements were performed on Cmod S7 FPGA boards (Xilinx XC7S25-1CSGA225C).

Negative capacitance FETs for energy efficient and hardware secure logic designs

Negative capacitance field effect transistors (NCFETs) have attracted good attention for energy efficient circuit designs. However, there are no clear design insights with NCFET based circuit designs for energy efficient and hardware secure applications. However, the lack of clear design insights make energy efficient and hardware secure NCFET circuit design more challenging. This paper presents important design insights and scope of NCFETs for energy efficient and hardware secure logic design at scaled supply voltages. Initially, NCFET device characteristics have been analyzed by varying the ferroelectric layer thickness (tfe) to identify optimum device performance window. At 40 nm technology node, NCFET device demonstrates enhanced characteristics for logic design with tfe in the range of 3 nm–5 nm due to steep subthreshold swing characteristics. NCFET with tfe of 5 nm exhibits 1.22 × higher ON current, 66 × lower leakage current and a SS of 50mV/dec compared to baseline MOSFET (tfe = 0 nm). Further, NCFET based static complementary inverter design exhibits better performance and higher energy efficiency compared to baseline MOSFET. NCFET inverter with tfe of 3 nm achieves optimum performance in terms of voltage transfer characteristics, differential gain, and noise margins. In addition, NCFET with tfe of 3 nm shows minimum energy consumption with the different supply voltages in the range of 0.6–0.8 V. Moreover, NCFET based buffer, logic gates and half-adder designs with tfe of 3 nm achieve approximately 3 × lower energy consumption compared to baseline designs. Apart from this, the NCFET designs exhibit 2 × higher ON current variations, 12 × higher inverter delay variations, and 3.1 × higher ring oscillator frequency variations compared to baseline designs against 5% process parameter variations at a supply voltage of 0.5 V. With the higher variations resulted from ferroelectric layer, NCFET demonstrate the potential and suitability towards the design of hardware security primitives like physically unclonable function (PUF) and true random number generator (TRNG).

Heterogeneous Functional Dielectric Patterns for Charge-Carrier Modulation in Ultraflexible Organic Integrated Circuits.

Flexible electronics have gained considerable attention for application in wearable devices. Organic transistors are potential candidates to develop flexible integrated circuits (ICs). A primary technique for maximizing their reliability, gain, and operation speed is the modulation of charge-carrier behavior in the respective transistors fabricated on the same substrate. In this work, heterogeneous functional dielectric patterns (HFDP) of ultrathin polymer gate dielectrics of poly((±)endo,exo-bicyclo[2.2.1]hept-ene-2,3-dicarboxylic acid, diphenylester) (PNDPE) are introduced. The HFDP that are obtained via the photo-Fries rearrangement by ultraviolet radiation in the homogeneous PNDPE provide a functional area for charge-carrier modulation. This leads to programmable threshold voltage control over a wide range (-1.5 to +0.2V) in the transistors with a high patterning resolution, at 2V operational voltage. The transistors also exhibit high operational stability over 140 days and under the bias-stress duration of 1800s. With the HFDP, the performance metrics of ICs, for example, the noise margin and gain of the zero-VGS load inverters and the oscillation frequency of ring oscillators are improved to 80%, 1200, and 2.5kHz, respectively, which are the highest among the previously reported zero-VGS -based organic circuits. The HFDP can be applied to much complex and ultraflexible ICs.

A robust Euclidean metric based ID extraction method using RO-PUFs in FPGA

Main problems in FPGA-based ring oscillator (RO) PUFs are that the RO frequencies are highly sensitive to operating conditions and other types of global variations. In addition, the RO frequencies are highly correlated by local variations. Therefore, in practice, conventional RO-PUF application schemes using Hamming distance normally require complex identification (ID) extraction algorithms and/or a large number of ROs to ensure a high level of uniqueness and reliability of the extracted IDs. In this work, we proposed a novel scheme of ID extraction based on Euclidean distances. Our proposed scheme stably and reliably generates the ID using a non-selective small number of ROs. Specifically, the generated IDs are mostly non-sensitive to global variables and operating conditions such as ambient temperature. In oppose to Hamming-based extraction, the close-frequencies ROs are normally removed to avoid flipping bits, our proposed scheme takes all those into account and simplifies the extraction process. Experiments on our available hardware have shown a very good level of reliability and uniqueness with ID collision rate is estimated less than 2×10−9.

Air-spacers as analog-performance booster for 5 nm-node N-channel nanosheet transistor

This work investigates the use of air-spacers as an analog-performance booster for nanosheet transistors (NSTs) at 5 nm node. The NSTs with air-spacers are evaluated across the design space for analog circuits. A fully calibrated three-dimensional technology computer-aided design platform was used for the device and mixed-mode circuit simulations. The use of air-spacers improves the output impedance (r o) from 974 kΩ to 1.32 MΩ, as well as the intrinsic gain (A v) from 90 to 118, for the NST with L g/W g = 240 nm/15 nm. The air-spacers also improve analog performance parameters such as the unit-gain frequency (f T) from 562 to 596 GHz; gain-frequency product from 4.76 to 5 THz; transconductance-frequency product from 2.11 to 2.22 THz; and the gain-transconductance-frequency product from 17.9 to 18.7 THz; for the NST with L g/W g value of 12 nm/15 nm. In addition, the discharge time (t d) also improves from 1.64 to 1.5 ns, for NST with L g/W g = 12 nm/120 nm. The oscillation frequency of a three-stage ring-oscillator is also reported to improve from 68.3 to 88.2 GHz by the use of air-spacers.

Supply Voltage Dependence of Ring Oscillator Frequencies for Total Ionizing Dose Exposures for 7-nm Bulk FinFET Technology

Total ionizing dose (TID) effects at the 7-nm bulk FinFET node are characterized through changes in ring oscillator (RO) frequencies and current as a function of V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> to model delay and power degradations in digital circuits. At the 7-nm node, tests show that gate delay decreased, and power consumption increased as TID increased. Percent increase in parameter degradations shows an inverse relationship with supply voltage, while percent increase in power consumption shows a direct relationship with supply voltage. Annealing at room temperature did not affect degradations. Circuit-level degradations for the 7-nm technology were less than 1% after TID exposure of 380 krad(SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ). These TID exposure results will provide insight to designers about circuit-level parameters of interest concerning the 7-nm technology node.

Characteristics of Stacked Gate-All-Around Si Nanosheet MOSFETs With Metal Sidewall Source/Drain and Their Impacts on CMOS Circuit Properties

In this brief, we computationally examine electrical characteristics of stacked gate-all-around Si nanosheet MOSFETs (GAA NS-FETs) with and without metal sidewall (MSW) source/drain (S/D) by increasing the number of channels (NCs) and their impacts on digital circuits. The ON-current ( I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> ) and circuit performances of the NS-FETs without the MSW S/D are limited to three channels due to the electrostatic potential decreasing from the top contacts to the bottom S/D side of NS-FETs; however, the MSW S/D can improve the I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> with increasing the NCs over three channels because of low resistivity of tungsten ( 5.6×10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-6</sup> Ω·cm) in the sidewall of S/D and then the circuit performances can be boost by the MSW S/D structure of the stacked GAA NS-FETs over three channels. For example, up to six channels of the NS-FETs with the MSW S/D, the frequency of ring oscillator is 57% increase, compared with the case without MSW S/D. The results of this study can be considered to design the S/D structure of the stacked GAA NS-FETs in emerging device technologies.

Reduction of Local Thermal Effects in FinFETs With a Heat-Path Design Methodology

In this letter, we propose a heat-path design for releasing heat confined in FinFETs. Conductive material stacks consisting of metals and vias on silicon can be good heat paths that lower junction temperature. However, they also increase parasitic capacitance, leading to degraded circuit performance. Therefore, we analyzed the impact of various heat paths with different metal stacks and locations on junction temperature, power consumption, and oscillation frequency of ring oscillators. Measurements of the oscillators showed that the optimized heat-path design had a 24.9%-lower change in junction temperature and a 1.53% higher oscillation frequency compared to a conventional layout. Furthermore, from thermally aware-compact model simulation results, we show that the proposed heat-path methodology can be more effective with the FinFET process than with the planar CMOS process.

Build-in compact and efficient temperature sensor array on field programmable gate array

Digital sensor arrays based on ring oscillators are used to monitor the temperature of Field Programmable Gate Array (FPGA) chips, but traditional sensor structures using binary frequency counters consume excessive hardware logic resources. This paper proposed a compact temperature sensor array that used low-decoding-complexity linear feedback shift registers (LFSR) as a frequency counter to efficiently count the ring oscillator frequency. We implemented an experimental system on a Spartan-6 FPGA, and the logic resource consumption of the entire system was 927 Look-Up-Tables (LUTs) with an overhead of only 10%. The single sampling time was approximately 40 μs. The proposed temperature sensor array has good temperature sensing capabilities, and the measured error is ±0.9°C(3σ).

Current Reused 8:1 Injection Locked Frequency Divider Using Unbalanced Ring Oscillator Frequency Divider

This paper proposes and analyzes a CMOS divide-by-8 injection locked frequency divider (ILFD) with a divide-by-2 ring oscillator stacked on a capacitive cross-coupled oscillator used as an LC divide-by-4 ILFD. The divide-by-8 ILFD in the TSMC $0.18~\mu \text{m}$ 1P6M CMOS process has a locking range from 15.5 GHz to 17.8 GHz at the power consumption of 10 mW. The varactorless divide-by-8 ILFD occupies a small area of $0.8044\times 0.72$ mm2. The ILFD can be used in divide-by-4 mode and has a locking range from 4.8 GHz to 10.6 GHz at the power consumption of 10.43 mW. The ring oscillator based frequency divider (FD) is designed with a pair of differential outputs so that the whole divide-by-8 ILFD provides differential output. The ring oscillator FD uses unbalanced component parameters to optimize the circuit performance and it supplies two unbalanced tail currents to the LC ILFD, which also provide unbalanced outputs despite the circuit topology is a symmetric one. The unbalanced approach offers design flexibility.

Modeling of the submicron CMOS differential ring oscillator for obtaining an equation for the output frequency

A symbolic expression that approximates the output frequency of the submicron differential ring oscillator, using the detailed transient behavior of the MOSFETs, is presented in this article. The circuit of the oscillator is simulated from 3-stage till 21-stage, with the range of output frequency from 0.3756 GHz till 2.6925 GHz. Later on, for verifying the similar functionality with different Beta ratios, a 7-stage differential ring oscillator is utilized. The average difference between the computed and the simulated values of the output frequency is found to be 1.98%, with TSMC 180 nm technology, when the value of Beta ratio was 2.3. The expression indicates that the output frequency is inversely proportional to the square of the device length. By including an empirical constant in the derived equation, the mathematical expression can be utilized for the hand calculations, for obtaining the output frequency of the differential ring oscillator.

A Self-Calibrated 2-bit Time-Period Comparator-Based Synthesized Fractional-N MDLL in 22-nm FinFET CMOS

This article describes a synthesized fractional-N multiplying delay-locked loop (MDLL) implemented in Intel 22-nm FFL FinFET technology. A 2-bit time-period comparator (TPC) is proposed to adjust the ring oscillator frequency to suppress the spurs without introducing errors due to its inherent phase offset. A programmable delay is used to compare the periods of the MDLL output in time domain, reducing power consumption and making the design synthesizable. TPC 2-bit output achieves fast and robust locking without any initial calibration. The fractional multiplication ratio is achieved by using a digital-to-time converter (DTC) in the reference path with a replica of the digitally controlled oscillator (DCO) to automatically achieve a range of one DCO period. Any variation in DTC delay due to gain mismatch is corrected by a digital loop operating in the background. A detailed analysis of the small-signal model and noise of the proposed MDLL has also been presented. The core area of the synthesized design is 0.0052 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> while operating over the frequency range from 1.2 to 3.8 GHz. The integrated rms jitter is 2.74 ps, and the spurs are below -47 dBc measured at 3.6175 GHz. Fractional-N MDLL power consumption is 3.19 mW with the figure of merit (FOM) of -226.3 dB.

A PVT-Resilient, Highly-Linear Fifth-Order Ring-Oscillator-Based Filter

This paper introduces a new class of ring oscillator (RO)-based filters that address linearity and process variance limitation of existing RO-based filters. A highly-linear process-tolerant RO filter topology is achieved by imitating the widely known active-RC topology in the phase domain. We propose utilizing a set of frequency detectors (FDs) and phase detectors (PDs) to extract both the frequency and phase information of an inverter-based RO to synthesize active filters in a way similar to integrator-based active-RC filters, which are synthesized using a set of capacitors and resistors, respectively. A zero compensation technique is proposed to extend the achievable bandwidth of the proposed topology. Also, a delay-locked loop (DLL)-based tuning scheme is introduced to achieve resilience over PVT variations. A prototype 5th-order, 2–22 MHz continuous-time Butterworth filter is presented in 130 nm CMOS technology to demonstrate the proposed topology. The filter consumes 6.2–8.9 mA from a 1 V supply and achieves 26.2 dB in-band IIP3. The filter achieves bandwidth variation less than ±3.5% over a temperature range of −40 °C to 85 °C and supply voltage range of 0.9–1.2 V.

Improved digital performance of charge plasma based junctionless C-FinFETs at 10 nm technology node and beyond

This paper investigates the digital performance of novel charge plasma based complementary (CPJL) FinFET inverters in terms of low and high noise margins, logic swing LS, DC power consumption PDC, rise tr and fall tf times, and propagations delay at both 10 and 7 nm technology nodes. In addition, their performance is compared with equivalent junctionless (JL) CFinFET inverters. Obtained results are physically analyzed including quantum–mechanical effects. Furthermore, the oscillation frequency of a three-stage ring oscillator constructed with CPJL-CFinFETs is computed, and compared with their JL-CFinFET counterpart. Our findings reveal that while dissipating less OFF-state power, tr and tf of the proposed CPJL inverter exhibit significant reduction of ~73.92% and ~79.82%, respectively, relative to its equally sized JL inverter value at 10 nm technology node. Moreover, the oscillation frequency of a three-stage ring oscillator (RO) built with CPJL inverters exhibits ~323.75% enhancement compared to its JL RO at 10 nm node.

Mismatch of Ferroelectric Film on Negative Capacitance FETs Performance

In this article, we analyze the impact of process variations of the ferroelectric film on the performance of the negative capacitance field-effect transistor (NCFET). Variations of the ferroelectric layer area (resulting from the variation of the transistor dimension sizes and the edge-effect), the ferroelectric layer thickness, the polarization, and the coercivity are taken into consideration to evaluate the impact on the NCFET performance. These results can serve as a guideline to improve both the circuit performance and yield for analog and digital circuits. To showcase this ability, the influence of these variations on the oscillating frequency of a five-stage ring oscillator and the mirroring current of a current mirror are analyzed. The results show that the distribution of the standard derivation of the oscillating frequency is 1.9 MHz on condition of ${T}_{\text {FE}}={14}$ nm, ${W}_{\text {P}}/{L}_{\text {P}}={1}~\mu \text{m}$ /45 nm, and ${W}_{\text {N}}/{L}_{\text {N}}={500}$ /45 nm, and the standard derivation of the mirroring current is $0.17~\mu \text{A}$ on condition of ${W}={1}\,\,\mu \text{m}$ , ${L}={500}$ nm, and ${T}_{\text {FE}}={20}$ nm.

Estimation of frequency and amplitude of ring oscillator built using current sources

Abstract In this paper a method is proposed to derive an equation for the oscillation frequency and amplitude of a ring oscillator built using two different current sources. Taking into consideration the transistor’s region of operation, the proposed method estimates the variation in oscillation frequency because of externally added load capacitance, supply voltage and number of stages. The analytical model so proposed is justified using 0.18 μm and 0.09 μm CMOS technology for a 5 stages ring oscillator. Indeed, the estimated oscillation frequency agrees with the simulated one, while the error was within 5%.

Impact of Interface Traps on Negative Capacitance Transistor: Device and Circuit Reliability

In this work, we investigate the impact of Si-SiO2 interface traps on the performance of negative capacitance transistor, which is a promising emerging technology that aims at achieving a steep sub-threshold slope. Interface traps induced degradation is well known to be one of the major concerns when it comes to reliability. We focus on investigating the impact of different interface trap concentrations on the figures of merit of both the devices and circuits. Our investigation is performed using TCAD models, which are well calibrated against 14nm production quality FinFETs. This allows accurate analysis and modeling of the impact of NC on the electric field across the SiO2 layer. Then, the industry compact model of FinFET (BSIM-CMG) is fully calibrated to reproduce TCAD data. In addition, a physics-based NC model is integrated and solved self-consistently within the BSIM-CMG model in which TCAD data of NC-pFinFETs and NC-nFinFETs are also well matched. This allows studying how interface traps induced degradation can impact circuits. Our results demonstrate that the amplified electric field across the SiO2 layer within NC-pFinFET due to NC effect leads to a higher interface trap concentration. This, in turn, results in a larger degradation in the NC-pFinFET compared to its pFinFET counterpart – when both of these devices are operated at the same nominal supply voltage of the 14nm node. However, at the same interface trap concentration, the NC-pFinFET always exhibits less degradation than the baseline pFinFET due to the former’s better electrostatic integrity on account of voltage amplification effect. With respect to circuits, we study both Ring Oscillator (RO) and 6-T SRAM cell circuits. We show how the frequency of RO in the case of NC-FinFET is always less impacted by interface trap induced degradations compared to its counterpart FinFET-based RO. For 6-T SRAM cell, we demonstrate how the key reliability metrics such as hold noise margin, read noise margin, and write noise margin are also less impacted by the induced degradations in NC-FinFET SRAMs compared to the baseline FinFET SRAMs. This is because of the much better electrostatic integrity that NC provides.

Improvement of oscillation characteristics of ring oscillator through photoconductivity and dielectric constant of photorefractive materials

The intensity of oscillation and the oscillation frequency shift are two most important parameters that characterize the performance of a photorefractive ring oscillator. In this paper, the effect of photoconductivity and dielectric constant of photorefractive (PR) materials on these parameters has been studied in case of non-degenerate two-wave mixing in PR materials. It has been found that for a given value of photoconductivity of PR material, the highly reflecting ( $$ R > 90\% $$ ) cavity mirrors are much effective parameter as compared to the other parameters (frequency detuning, absorption strength, energy beam coupling strength and dielectric constant) for the enhancement of the intensity of oscillation in the oscillator. Also, the magnitude of oscillation frequency of the photorefractive ring oscillator (PRO) can be increased by inserting PR crystal of lower dielectric constant ( $$ \varepsilon < 7.0 $$ ), higher photoconductivity ( $$ \sigma_{\text{p}} > 500\,{\text{pS/cm}} $$ ) and highly reflectivity ( $$ R > 90\% $$ ) cavity mirrors provided that the cavity-length detuning $$ \left( {\frac{\Delta \varGamma }{\pi } > 1.0} \right) $$ of the oscillator is higher. This means that the intensity and frequency of the PRO could be controlled by the dielectric constant and photoconductivity of a PR crystal which would greatly improve performance of a PRO and their applications based on these photorefractive ring oscillators such as wave front color conversion, optical limiting, optical computing and beam cleanup.

Recycled FPGA Detection Using Exhaustive LUT Path Delay Characterization and Voltage Scaling

Field-programmable gate arrays (FPGAs) have been extensively used because of their lower nonrecurring engineering and design costs, instant availability and reduced visibility of failure, high performance, and power benefits. Reports indicate that previously used or recycled FPGAs are infiltrating the electronics’ supply chain and making the security and reliability of the critical systems and networks vulnerable. Current recycled integrated circuit (IC) detection procedures include parametric, functional, and burn-in tests that require golden or reference data. Besides, they are time consuming, require expensive equipment, and do not focus on FPGAs. In this article, we propose two recycled FPGA detection methods based on supervised and unsupervised machine learning algorithms. We develop a sophisticated ring oscillator (RO) design to exploit the degradation of lookup tables (LUTs) and use them in the proposed methods. In the supervised method, a one-class classifier is trained with RO frequencies, kurtosis, and skewness data obtained from unused FPGAs, which differentiates unused and aged FPGAs. The unsupervised method uses $k$ -means clustering and Silhouette value analysis to detect suspect recycled components with very little (if any) golden information. In addition, we introduce a voltage scaling-assisted RO frequency measurement technique that improves the classification. The proposed methods are examined for Spartan-3A and Spartan-6 FPGAs, and the result shows that both methods are effective in detecting recycled FPGAs, which experience accelerated aging for at least 12 h equivalent to 70 days in real-time age.