Improved digital performance of charge plasma based junctionless C-FinFETs at 10 nm technology node and beyond

Abstract

This paper investigates the digital performance of novel charge plasma based complementary (CPJL) FinFET inverters in terms of low and high noise margins, logic swing LS, DC power consumption PDC, rise tr and fall tf times, and propagations delay at both 10 and 7 nm technology nodes. In addition, their performance is compared with equivalent junctionless (JL) CFinFET inverters. Obtained results are physically analyzed including quantum–mechanical effects. Furthermore, the oscillation frequency of a three-stage ring oscillator constructed with CPJL-CFinFETs is computed, and compared with their JL-CFinFET counterpart. Our findings reveal that while dissipating less OFF-state power, tr and tf of the proposed CPJL inverter exhibit significant reduction of ~73.92% and ~79.82%, respectively, relative to its equally sized JL inverter value at 10 nm technology node. Moreover, the oscillation frequency of a three-stage ring oscillator (RO) built with CPJL inverters exhibits ~323.75% enhancement compared to its JL RO at 10 nm node.