Performance of Ge p-channel junctionless FinFETs for logic applications

Abstract

In this paper, we report an investigation of the performance of a Ge junctionless (JL) p-FinFET and compare it with that of a Si JL p-FinFET for logic applications. CMOS inverters are built with such Ge p-FinFETs and Si n-FinFETs for three different technology nodes as per the ITRS roadmap. Transient analysis of CMOS inverters is made to evaluate the logic performance parameters such as rise time and fall time. Then, mixed-mode circuit simulations are performed for a three-stage ring oscillator, build with such CMOS inverters, to evaluate frequency of oscillation and propagation delay. Our investigations reveal that CMOS circuits built with Ge JL p-FinFETs outperform their equally sized all Si counterpart. Reduction of ~ 70% in the rise time for the CMOS inverters and improvement of more than 75% in the frequency of oscillation for the ring oscillators are observed for all three technology nodes when Ge p-channel devices are used.