Abstract
In this paper, a one-to-one comparison of the logic performance is made between CMOS circuits built with bulk junctionless (JL) FinFETs and that with SOI JL FinFETs for three different technology nodes as per the ITRS roadmap. For such comparison: (i) the rise time and fall time are evaluated from the transient analysis of a CMOS inverter,(ii) the propagation delay per stage for a three-stage ring oscillator is estimated from its frequency of oscillation, and (iii) the static noise margin of a 6 T SRAM cell is evaluated from its butterfly plot. A three-dimensional numerical device and mixed-mode circuit simulator is used for the performance estimation. CMOS circuits implemented with bulk JL devices are found to have comparable logic performance with their SOI JL counterparts.
Sign-in/Register to access full text options 
Free) 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a call
