High-Speed 501-Stage DCFL GaN Ring Oscillator Circuits

Abstract

Direct-coupled field-effect transistor (FET) logic inverters and 501-stage ring oscillators (ROs) are fabricated using highly scaled GaN heterojunction FET with gate lengths of 20 and 40 nm. A 40-nm gate-length E/D inverter has logic-low and logic-high noise margins of 0.465 and 1.59 V, respectively, and a logic voltage swing of 2.38 V measured at Vdd = 2.5 V. The corresponding 40-nm 501-stage RO frequency and stage delay are 0.067 GHz and 15 ps, whereas the frequency and stage delay of a 20-nm RO are 0.133 GHz and 7.5 ps. The yield of the 20-nm 501-stage RO circuits is 52% across a 3-in diameter wafer. With 1006 transistors, the 501-stage ROs represent the highest level of transistor integration to date for a GaN circuit, whereas the stage delay is the shortest reported for a GaN digital circuit.