Forward Voltage Drop Research Articles

Static and Dynamic Performance Prediction of Ultrahigh-Voltage Silicon Carbide Insulated-Gate Bipolar Transistors

The performance of theoretical ultrahigh-voltage power semiconductor devices has been predicted by means of numerical simulations using the Sentaurus technology computer-aided design tool. A general silicon carbide punch-through insulated-gate bipolar transistor (IGBT) structure has been implemented with suitable physics-based models and parameters to reflect the device characteristics in a wide range of device blocking voltages from 20 to 50 kV. The models for 20 kV class IGBTs have been implicitly validated by means of published experimental results. Mixed-mode simulations were performed that predicted total switching energy loss densities of 335, 629, 906, and 999 mJ/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> for 20, 30, 40, and 50 kV class devices, respectively, at 25 °C, JC = 20 A/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , and an ambipolar carrier lifetime of 20 μs. While the IGBT on-state forward voltage drop reduces, the switching losses increase with higher charge-carrier lifetime for a given current density (e.g., 20 A/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ). The large span of simulation results will be used as an input support to the design of future high-power converters.

A Study on 4H-SiC LIGBT with Dual Emitter for High Voltage Driver IC

This paper describes a lateral insulated gate bipolar transistor (LIGBT) with dual emitter structure in 4H-silicon carbide (4H-SiC). The electrical characteristics of the dual-emitter LIGBT are better than those of the conventional 4H-SiC LIGBT. The dual-emitter structure has an additional emitter between the emitter and the collector in the conventional LIGBT structure. The addition of the emitter can significantly improve forward voltage drop, on-resistance and current driving characteristics. Experimental results show that the 4H-SiC dual-emitter LIGBT has lower forward voltage drop, lower on-resistance and a higher current driving capability than the conventional 4H-SiC LIGBT.

Analysis of an efficient interleaved ultra‐large gain DC–DC converter for DC microgrid applications

This study deals with steady-state analysis and control of a step-up interleaved winding cross-coupled inductor DC–DC converter with high voltage gain and reduced voltage stress across semiconductors using voltage multiplier cells (VMCs). Because of the interleaved scheme, the thermal stress is reduced and the input current ripple is minimised. The leakage energy is recycled by passive lossless clamp circuit to the output. Meanwhile, the voltage stress across the semiconductors is substantially low. Hence, MOSFETs with less ON-state resistances and diodes with a less forward voltage drop can be utilised that improves the circuit performance. The operation principle and the steady state are discussed. Small-signal modelling of the proposed converter is derived via state-space averaging technique and a dual loop controller for output voltage regulation is designed. The adopted strategy utilises a fast dynamical inner loop to control the input current and an outer loop for the output voltage regulation. Finally, a 1 kW prototype with 60 V–1 kV voltage conversion is fabricated and tested to probe the carried analysis.

Wide-Range Prediction of Ultra-High Voltage SiC IGBT Static Performance Using Calibrated TCAD Model

In this paper, a technology computer-aided design (TCAD) model of a silicon carbide (SiC) insulated-gate bipolar transistor (IGBT) has been calibrated against previously reported experimental data. The calibrated TCAD model has been used to predict the static performance of theoretical SiC IGBTs with ultra-high blocking voltage capabilities in the range of 20-50 kV. The simulation results of transfer characteristics, IC-VGE, forward characteristics, IC-VCE, and blocking voltage characteristics are studied. The threshold voltage is approximately 5 V, and the forward voltage drop is ranging from VF = 4.2-10.0 V at IC = 20 A, using a charge carrier lifetime of τA = 20 μs. Furthermore, the forward voltage drop impact for different process dependent parameters (i.e., carrier lifetimes, mobility/scattering and trap related defects) and junction temperature are investigated in a parametric sensitivity analysis. The wide-range simulation results may be used as an input to facilitate high power converter design and evaluation. In this case, the TCAD simulated static characteristics of SiC IGBTs is compared to silicon (Si) IGBTs in a modular multilevel converter in a general high-power application. The results indicate several benefits and lower conduction energy losses using ultra-high voltage SiC IGBTs compared to Si IGBTs.

1.2 kV, 10 A, 4H-SiC Bi-Directional Field Effect Transistor (BiDFET) with Low On-State Voltage Drop

Bidirectional power switches are used in matrix-or cyclo-converters and in multistage inverter circuits to facilitate high-frequency AC-to-AC conversion. A new 1.2 kV bidirectional MOSFET (BiDFET) with low on-resistance is achieved and demonstrated using two discrete SiC power MOSFET bare die chips, packaged within a four-terminal custom-designed module. Static and dynamic characterization has been carried out to inspect the on-state and switching behaviour of the BiDFET. The BiDFET is shown to have a low forward voltage drop of 0.6 V at a current of 10 A, which is more than 2.5x smaller than previous Si IGBT and SiC MOSFET based bidirectional switch implementations.

An Improved V CE–E OFF Tradeoff and Snapback-Free RC-IGBT With P⁺ Pillars

In this article, a novel snapback-free reverse-conducting insulated-gate bipolar transistor (RC-IGBT) with P+ pillars at the collector side (PPC) is proposed and investigated by TCAD simulations. This structure features the P+ pillar structure at the side of collector and exits a gap of N-buffers above N+ collector. The P+ pillars increase the distributed resistance below the buffer layer during turn-on transient, show bipolar mode, and eliminate the snapback phenomenon. Accordingly, the structure eliminates the snapback phenomenon with a smaller half-cell pitch of ${10}~\mu \text{m}$ , making that the device is more reliable and suitable for parallel connection. For the same forward voltage drop, the turn-off loss of the PPC structure is reduced by 34%.

Mobility Models Based on Forward Current-Voltage Characteristics of P-type Pseudo-Vertical Diamond Schottky Barrier Diodes.

Compared with silicon and silicon carbide, diamond has superior material parameters and is therefore suitable for power switching devices. Numerical simulation is important for predicting the electric characteristics of diamond devices before fabrication. Here, we present numerical simulations of p-type diamond pseudo-vertical Schottky barrier diodes using various mobility models. The constant mobility model, based on the parameter μconst, fixed the hole mobility absolutely. The analytic mobility model resulted in temperature- and doping concentration-dependent mobility. An improved model, the Lombard concentration, voltage, and temperature (CVT) mobility model, considered electric field-dependent mobility in addition to temperature and doping concentration. The forward voltage drop at 100 A/cm2 using the analytic and Lombard CVT mobility models was 2.86 and 5.17 V at 300 K, respectively. Finally, we used an empirical mobility model based on experimental results from the literature. We also compared the forward voltage drop and breakdown voltage of the devices, according to variations in p- drift layer thickness and cathode length. The device successfully achieved a low specific on-resistance of 6.8 mΩ∙cm2, a high breakdown voltage of 1190 V, and a high figure-of-merit of 210 MW/cm2.

Experimental Evaluation of SiC Mosfets in Comparison to Si IGBTs in a Soft-Switching Converter

Silicon-carbide (SiC) mosfet s have shown superior characteristics to Si IGBTs, bringing in significant performance improvement such as enabling more compact, higher efficiency converters that are not feasible with conventional Si IGBTs. Currently, there is a lack of systematic and conclusive investigation into soft-switching inverters using SiC mosfet s in comparison to Si IGBTs. This article, therefore, presents a comparative evaluation of a soft-switching inverter, i.e., the auxiliary resonant commutated pole inverter (ARCPI) using SiC mosfet s or Si IGBTs. The switching transition, switching device current stress, neutral point ripple current, electromagnetic interference (EMI), efficiency, and cost are compared on identical ARCPI setups, i.e., with the same printed circuit boards and under identical driving conditions (gate drivers). Experimental results show that the ARCPI using SiC mosfet s has better performance than that using Si IGBTs due to its faster switching speed. First, the ARCPI using SiC mosfet s performs full zero-voltage switching and the switching transition behavior is more predictable. Unlike Si IGBTs, SiC mosfet s have no turn- off tail current and forward voltage drop during switching transitions. Second, the ARCPI using SiC mosfet s endures less current stress and smaller ripple current in dc-link capacitors. Third, the ARCPI using SiC mosfet s exhibits better EMI performance and higher efficiency. Specifically, a maximum 20 dB μ V harmonic reduction can be achieved around 800 kHz and a 3.1% improvement in efficiency can be achieved at 6 kW.

A Novel ZVS High-Step-Up Converter With Built-In Transformer Voltage Multiplier Cell

This article proposes a novel interleaved high-step-up dc-dc converter with zero voltage switching (ZVS). Through a built-in transformer voltage multiplier cell (VMC) the high voltage conversion ratio is achieved without the narrow duty. By applying active clamp scheme, all of the power MOSFETs are switched with ZVS which minimizes the switching losses of the proposed converter. Besides the voltage stress across the switches is decreased and can be controlled by the built-in transformer turns ratio enabling utilization of low on-state resistance and low forward voltage drop semiconductors. Due to the interleaved structure, the input current ripple is minimized and the thermal stress is shared between the phases. Meanwhile, the charge balance of the capacitors give rise to equal current sharing performance for the two input inductors. All of these factors reduce the power losses and improves the performance of the proposed converter. Finally, in order to verify the operation of the proposed converter, a 35-V input voltage to 500-V output voltage prototype with the rated power of 1 kW is fabricated and tested in the laboratory.

A Novel Interleaved High Step-Up Converter With Built-In Transformer Voltage Multiplier Cell

In this article, we propose a novel interleaved high step-up converter. The proposed converter integrates the built-in transformer voltage multiplier cell (VMC) to the interleaved boost converter with voltage lift capacitor. The voltage gain is increased by both of the turns ratio of the built-in transformer and the voltage lift capacitor. Hence, there is no need to operate the converter around unity duty cycles to obtain high voltage gains. Meanwhile, the voltage stress across semiconductors is reduced considerably, facilitating the utilizing of mosfets with low on-state resistance and diodes with low forward voltage drop decreasing the conduction losses. The leakage inductance of the built-in transformer not only provides zero current switching (ZCS) for mosfets but also controls the falling current rate of the diodes alleviating the reverse current recovery problem. In addition, the energy of the leakage inductance is recycled by the clamp capacitor avoiding high spikes across switches. In comparison with the recently published converters, the proposed converter introduces all of the abovementioned advantages with a low number of components that make it an interesting solution for high efficiency and high step-up applications. Finally, a 40-V to 580-V prototype with 930 W power is fabricated to explore the merits of the proposed converter.

Investigation on 4H-SiC gate turn-off thyristor with direct carrier extraction access to drift region for power conversion applications

4H-SiC gate turn-off (GTO) thyristor offers extraordinary advantages over its counterparts in handling ultra-high voltage electric power conversion applications because of its relatively low forward voltage drop at high conduction current density. Besides, though the SiC thyristors never suffer from long carrier liftime induced large switching loss like Si thyristors, the peak temperature rise rather than dynamic avalanche breakdown is blamed for the safe operation area (SOA) failure, making further reduction of power loss in SiC GTOs even more important. In this paper, a 20 kV SiC GTO with direct carrier extraction access to its drift region (DA-GTO) is investigated to explore the benefit this structure could bring for SiC thyristors, namely achieving smaller switching loss and/or potential larger SOA with slight sacrifice in forward voltage drop at high current. The structure is formed by interleaved P+ ion implantation into part of the thin N-injector layer based on conventional 20 kV SiC GTO. The SiC DA-GTO operates in BJT mode at low current, and in GTO mode with low forward voltage drop at high current. During turn-off process, it offers a direct current path to quickly sweep out the excess carriers in the P-drift region, thus speeds up the turn-off process and decreases the turn-off loss. Simulation results show that its turn-off loss reduces by 37.4%, contributing to 12.6% reduction in total power loss, compared with SiC GTO. Therefore, SiC DA-GTO is a very promising choice for next-generation power conversion systems.

Research and Development of 1200V 4H-SiC Trench JBS Diode

This paper introduces the design and fabrication process of 1200V SiC trench Junction Barrier Schottky (JBS) diode, and tests the performance of the diode. The cell and terminal of diode structure both adopt trench structure, by simulation and early stage, the structural parameters of device cell and terminal structure are determined, and the fabrication of 1200V SiC trench JBS diode is completed through an intact technological process. The test results show that the leak current of the device under 1200V at room temperature is about 0.36uA, when the current is 20A, the forward voltage drop is 1.53V.

Novel SOI LIGBT with fast‐switching by the electric field modulation

A novel silicon-on-insulator lateral insulated gate bipolar transistor (SOI LIGBT) is proposed and investigated in this work. The device features a single-step buried oxide (SSBO) structure formed on the silicon-on-insulator (SOI) layer. The SSBO structure introduces a high electric field peak by the electric field modulation to modulate electric field distributions. Therefore, the proposed SOI LIGBT can maintain the high breakdown voltage (BV) while shortening the length of drift region, which achieves the decreased total number of stored carriers during the turn-on and fast depletion of drift region during the turn-off. As the simulation results show, under the same BV of 98 V, the drift region length of the proposed SOI LIGBT is 4.4 μm, which is much shorter than that of the conventional SOI LIGBT of 12.0 μm. So the turn-off time of SSBO SOI LIGBT is 76.6% lower than that of the conventional SOI LIGBT at the same forward voltage drop of 1.72 V. It shows that the tradeoff between forward voltage drop and turn-off time can be significantly improved.

Gate Current and Snapback of 4H-SiC Thyristors on N+ Substrate for Power-Switching Applications

High-power switching applications, such as thyristor valves in a high-voltage direct current converter, can use 4H-SiC. The numerical simulation of the 4H-SiC devices requires specialized models and parameters. Here, we present a numerical simulation of the 4H-SiC thyristor on an N+ substrate gate current during the turn-on process. The base-emitter current of the PNP bipolar junction transistor (BJT) flow by adjusting the gate potential. This current eventually activated a regenerative action of the thyristor. The increase of the gate current from P+ anode to N+ gate also decreased the snapback voltage and forward voltage drop (Vf). When the doping concentration of the P-drift region increased, Vf decreased due to the reduced resistance of a low P-drift doping. An increase in the P buffer doping concentration increased Vf owing to enhanced recombination at the base of the NPN BJT. There is a tradeoff between the breakdown voltage and forward characteristics. The breakdown voltage is increased with a decrease in concentration, and an increase in drift layer thickness occurs due to the extended depletion region and reduced peak electric field.

An effective method for evaluating thermal parameters of diode-based thermal sensors

Diode-based thermal sensors have a wide range of applications in industry and civil. Thermal conductance, heat capacity and thermal time constant are three main thermal parameters of diode-based thermal sensors. Extracting their thermal parameters is of great importance in evaluating sensors’ performance. In this work, an effective electrical circuit is developed to determine these thermal parameters of diode-based thermal sensors. The method takes advantage of self-heating effect of sensors and involves the measurement of time dependent forward voltage drop of sensors under a square-pulse voltage. The technique to accurately extract thermal parameters from the circuit is analyzed carefully, and its validity is verified experimentally using an infrared focal plane array with series diodes. The experimental results are in good agreement with the theoretical analyses of structure. The measurement technology is very easy for engineers to grasp.

Passive Resonant Level Shifter for Suppression of Crosstalk Effect and Reduction of Body Diode Loss of SiC MOSFETs in Bridge Legs

Due to the presence of parasitic elements in switching devices and circuit realization, crosstalk phenomenon in bridge-leg configurations is unavoidable. A passive resonant level shifter that can suppress the effect of the crosstalk and deliver a low off-state gate-source voltage to reduce the forward voltage drop of the body diode of SiC mosfets is presented. The circuit is composed of two parts. The first one is a resistor-capacitor-diode (RCD) level shifter that delivers a static negative off-state gate-source voltage to the mosfets. The voltage level is designed to be close to zero, so that the forward voltage drop of the body diode is lowered. The second one is a series resonant tank circuit. It generates short voltage pulses to counteract the voltage pulses caused by the crosstalk. The gate-source voltage can then be maintained at a level below the threshold voltage of the mosfets. The proposed level shifter does not require any active devices or additional supply. It can be applied readily to commercially available gate drivers. A passive resonant level shifter module for four SiC mosfets in a 1-kW H-bridge inverter has been built and evaluated. Detailed performance comparison with the RCD level shifter will be given.

A High-Efficiency Low-Power Rectifier for Wireless Power Transfer Systems of Deep Micro-Implants

In this article, the so-called bootstrapping rectifier (BSR) proposed by Hashemi et al. is re-analyzed, and a novel high-efficiency low-power rectifier called Opto-Coupled Dynamic Gate-Control (OCDGC) rectifier is presented based on the bootstrapping structure. Circuit analysis of BSR shows that the rectifier design has inherent problems that cause a high forward voltage drop and limit its power conversion efficiency (PCE). The BSR is simulated and fabricated in TSMC 0.18 μm process, and both simulation and experiment results prove the analysis. Inspired by the idea of bootstrapping structure, the presented OCDGC rectifier utilizes an opto-coupler to control the on-off switching of the active diode to maximize input power and prevent reverse leakage. A feedback loop is also introduced in the rectifier to limit the forward voltage drop. The proposed design is simulated in the TSMC 0.18 μm process. Simulation results show that, with a 3 MHz input, OCDGC rectifier is able to achieve more than 80% PCE at an input power down to 0.55 mW and achieve a forward voltage drop less than 0.1 V. More than 20% PCE improvement is achieved compared with the PCE of BSR.

Forward Voltage Drop Induced by an Abnormal Threading Dislocation Aggregation in 4H-SiC GTO Devices.

An abnormal star-like defect was found on the failed SiC gate turn-off thyristor (GTO) devices after metal removal and KOH etching at 450 °C in this work. It is of extraordinary larger size of 210–580 µm, even much larger than the etch pit of a micropipe in 4H-SiC. In addition, the abnormal star-like defect, exhibiting the consistent orientation with the six-fold symmetry of silicon carbide, was found to consist of several penetrating dislocations with the help of a LEXT OLS4000 3D laser confocal microscope. These abnormal star-like etch pits can severely reduce the forward blocking characteristic of GTOs, while exerting insignificant influence on the forward current-voltage characteristics between anode and gate electrode of the 4H-SiC GTO devices. Interestingly, the relationship between forward voltage drop and dislocation density is affected by the abnormal star-like defect. A regular increase of forward voltage drop at 100 A/cm2 was observed with the increasing dislocation density, while this correlation disappears in the presence of an abnormal star-like defect.

Improved Bootstrap Methods for Powering Floating Gate Drivers of Flying Capacitor Multilevel Converters and Hybrid Switched-Capacitor Converters

A major challenge in the implementation of flying capacitor multilevel (FCML) converters and hybrid switched-capacitor (SC) converters is providing gate drive power to the large number of floating switches. A common solution uses isolated dc/dc converters, which are bulky, expensive, and energy inefficient. To design more compact and efficient gate drive power supply circuits, five methods are presented and compared in this article: bootstrap at deadtime, cascaded bootstrap with low-dropout (LDO) regulator, double charge pump, gate-driven charge pump, and synchronous bootstrap. By leveraging the inherent properties of multilevel converters, these methods can overcome the limitation of conventional bootstrap method (diode forward voltage drop) and make it possible to transfer ground-referenced power to all of the floating switches for any FCML or hybrid SC converters. Compared with the typical isolated dc/dc solution, these methods have simple structure and operating principle and can be implemented with a small number of diodes, capacitors, and LDOs. Experimental results show that an example power supply circuit can cut the size of the power stage of a state of the art seven-level FCML converter by half at 1/6 of the cost.

Developing the Guard Ring Topology of Power Silicon Diodes with a Blocking Voltage of up to 6.7 kV

High-voltage fast recovery diodes (FRDs) are characterized by a small forward voltage drop and low power dissipation. The main characteristics of such diodes is the reverse blocking voltage or the breakdown voltage. The aim of this work is to develop a guard ring topology allowing us to obtain the maximum possible blocking voltage of the diode and definite localization of the breakdown place under the conditions of the standard technological processes and without using new materials or substrates. The topology of the high-voltage part of silicon fast recovery power diodes is developed to obtain the maximum reverse blocking voltage. The calculations are carried out in the TCAD environment in the structure editor of which we included a program for the automatic creation of device models with dimensions of about several millimeters. The arrangement of guard rings is calculated according to the proposed principle allowing us to obtain power diodes with different breakdown voltages. The topology is developed so that the breakdown occurs under the edge of the active region, which guarantees the absence of catastrophic failures of the device. Power fast recovery diodes manufactured according to the proposed topology have the maximum reverse blocking voltage within the range of 3.3–6.7 kV, which indicates the reliability of the calculation methodology.