Flip Chip Technology Research Articles

Cluster based dynamic area-array I/O planning for flip chip technology

With the recent advances in chip fabrication and the ever increasing demand for high performance circuits, the conventional peripheral I/O placement techniques fail to meet the stringent requirements of the chip design. As a result, the existing algorithms result in excessive wire length, long critical paths, and computationally expensive and intensive. In this paper we introduce a new area I/O placement technique that co-designs the chip and package. The present algorithm is non-iterative and constructive. It assigns the functional blocks and primary inputs/outputs simultaneously and considers the package imposed constraints during the planning stage. The algorithm progresses in stages. At each stage, the functional blocks are placed on the chip on the fly and grouped together to form clusters. Various criteria like primary input net span and adjacency of clusters are taken into consideration for the placement of functional blocks. Experimental results showed that due to the non-iterative property, the proposed algorithm achieved 10× speedup over the traditional algorithms while obtaining a planning solution with optimal wire length and minimized delay.

Reliability Testing and Modeling of Anisotropic Conductive Adhesive Joints Under Temperature Cycling Test

The use of anisotropic conductive adhesives (ACAs) in flip-chip interconnection technology has several advantages compared to solders with underfills. However, when ACAs are used with organic substrates, their reliability may cause problems. Temperature cycling testing can be used to study the effect of fluctuating temperatures on the reliability of ACA joints. However, this is fairly time consuming. If modeling can be utilized in the evaluation of reliability, significant time savings can be achieved. In this paper, the prospects of using shear stress modeling in predicting the reliability of two different anisotropic conductive adhesive films (ACFs) with an organic FR-4 substrate in temperature cycling testing are examined. Finite element models were made for the test structures. Stresses and strains during the cycling tests ae calculated. To estimate the validity of the models, experimental testing is also done. Test samples with two different ACFs are tested in a temperature cycling test where the temperatures vary from -40°C to 125 °C. Testing is carried out for 10000 cycles. In addition, failure analysis is conducted on the test samples. To model the test samples accurately, the material properties of the ACFs are tested using a dynamic mechanical analyzer and a thermomechanical analyzer. The results of the modeling are compared with those of the experimental tests by comparing typical failure locations, failure modes, and the failure order of the test samples with different ACFs. According to the modeling, the highest shear stress seems to indicate the failure location. In addition, it seems that shear stress models can be used to rank ACF flip-chip joints in the order of the anticipated failure times. On the other hand, normal stress and strain models seem to describe failure mechanisms different from that observed in the experimental tests, and they are observed to be impractical for our purposes. Delamination, which may be one manifestation of failure mechanisms related to shear stress, is observed in all samples with ACF1. However, as no delamination is found in the samples with ACF2, it cannot be positively stated whether the failure mechanism of ACF2 joints is related to shear stress or not. If the samples with different ACFs have different failure factors, simple stress or strain models seem to be impractical for reliability studies, as the results of different models cannot be easily compared.

Three-Dimensional Thermomechanical Simulation of Fine-Pitch High-Count Ball Grid Array Flip-Chip Assemblies

Flip-chip technology is increasingly prevalent in electronics assembly [three-dimensional (3D) system-in-package] and is mainly used at fine pitch for manufacture of megapixel large focal-plane detector arrays. To estimate the reliability of these assemblies, numerical simulations based on finite-element methods appear to be the cheapest approach. However, very large assemblies contain more than one million solder bumps, and the optimization process of such structures through numerical simulations turns out to be a very time-consuming task. In many applications, the interconnection layer of such flip-chip assemblies consists of solder bumps embedded in epoxy filler. For such configurations, we propose an alternative approach, which consists in replacing this heterogeneous interconnection layer by a homogeneous equivalent material (HEM). A micromechanical model for the estimation of its equivalent thermoelastic properties has been developed. The obtained constitutive law of the HEM was then implemented in finite-element software (Abaqus®). Thermomechanical responses of tested assemblies submitted to loads corresponding to manufacturing conditions have been analyzed. The homogenization–localization process allowed estimation of the mean values of stresses and strains in each phase of the interconnection layer. To access more precisely the stress and strain fields in these phases, two models of structural zoom, taking into account the real solder bump geometry, have been tested. The obtained local stress and strain fields corroborate the experimentally observed damage initiation of the solder bumps.

Preparation of a YAG:Ce phosphor glass by screen-printing technology and its application in LED packaging

A simple and practical method for preparing phosphor glass is proposed. Phosphor distribution and element analysis are investigated by optical microscope and field emission scanning electron microscope (FE-SEM). The phosphor particles dispersed in the matrix are vividly observed, and their distributions are uniform. Spectrum distribution and color coordinates dependent on the thickness of the screen-printed phosphor layer coupled with a blue light emitting diode (LED) chip are studied. The luminous efficacy of the 75 μm printed phosphor-layer phosphor glass packaged white LED is 81.24 lm/W at 350 mA. This study opens up many possibilities for applications using the phosphor glass on a selected chip in which emission is well absorbed by all phosphors. The screen-printing technique also offers possibilities for the design and engineering of complex phosphor layers on glass substrates. Phosphor screen-printing technology allows the realization of high stability and thermal conductivity for the phosphor layer. This phosphor glass method provides many possibilities for LED packing, including thin-film flip chip and remote phosphor technology.

Characters of multicomponent lead-free solders

In the process of electronic packaging, such as flip chip technology, under bump metallization (UBM) can be consumed gradually by solder during soldering. Then dissolution of Ni, Au and Cu from UBM into the solder may change the original solder to a multicomponent one especially under the trend of miniaturization. It is quite necessary to evaluate the properties of the multicomponent solders that have new composition after soldering. In this study, the microstructure, thermal and mechanical properties of five types of multicomponent lead-free solders, i.e. Sn–2Cu–0.5Ni, Sn–2Cu–0.5Ni–0.5Au, Sn–3.5Ag–0.5Ni, Sn–3.5Ag–1Cu–0.5Ni and Sn–3.5Ag–2Cu–0.5Ni (all in wt% unless specified otherwise) were investigated. Comparison with eutectic Sn–0.7Cu, Sn–3.5Ag and Sn–3.5Ag–0.7Cu solders was made. There was no obvious difference of the melting point between the multicomponent lead-free solders and the eutectic ones. For Sn–2Cu–0.5Ni solder, Cu6Sn5 and (Cu,Ni)6Sn5 intermetallic compounds (IMCs) formed. In the case of Sn–2Cu–0.5Ni–0.5Au, besides (Cu,Ni)6Sn5, (Cu,Au)6Sn5 and (Cu,Ni,Au)6Sn5 were also observed. The IMCs formed in Sn–3.5Ag–0.5Ni solder were Ag3Sn and Ni3Sn4. In both Sn–3.5Ag–1Cu–0.5Ni and Sn–3.5Ag–2Cu–0.5Ni solders, Ag3Sn and (Cu,Ni)6Sn5 were detected. The mechanism for the formation of the IMCs was discussed. Tensile test was also conducted. The fractography indicated that all of the multicomponent lead-free solders exhibited a ductile rupture.

Integrated 122-GHz Antenna on a Flexible Polyimide Substrate With Flip Chip Interconnect

A packaging solution for the integration of an MMIC and a thin film antenna into a single surface-mountable package is presented. It is based on an air cavity in the package base into which the MMIC is placed. All package-to-MMIC interconnects are routed through the antenna substrate and all connections are realized using flip chip technology. Thus wire bonds are eliminated within the whole package. A broadband flip chip interconnect is used to connect MMIC and antenna. As the antenna is situated above an air cavity, a large bandwidth is also achieved for the antenna. An antenna-in-package prototype is presented to demonstrate the feasibility of the assembly process and to test the antenna performance including the flip chip interconnect. The influence of an additional package cover is analyzed by measuring the antenna covered with two different lids.

The Distribution and Transport of Alpha Activity in Tin

The presence of alpha emitters in packaging materials poses an increased risk to device reliability as device size decreases and flip chip and 3D packaging technology becomes more widespread. Particularly troubling is the observation that alpha emission increases over time in some reported instances. Several experiments were conducted to examine alpha flux behavior in tin materials and determine the cause for the temporal alpha emissivity increase. The experiments determined the distribution of the alpha emitters within the material volume, and a mechanism based on microsegregation is presented to explain the nonuniform distribution. Data describing differential isotope distribution within tin are also presented, providing confirmation of 210Po transport within a solid tin matrix. The effects of micro-segregation and 210Po migration on alpha emissivity over time are discussed. Potential impacts from these mechanisms on alpha emissivity in packaging applications are presented.

Comparison of thermomigration behaviors between Pb-free flip chip solder joints and microbumps in three dimensional integrated circuits: Bump height effect

Packaging technology is currently transition from flip chip technology to three dimensional integrated circuits (3D ICs) to meet the requirements of consumer electronic products. Compared to flip chip technology, the dimension of microbumps in 3D ICs is shrunk by a factor of 10. In this study, the behaviors of thermomigration in Pb-free solders of flip chip and 3D ICs are presented. When the bump height is 100 μm in the flip chip samples, the Sn protrusion was observed at the hot end and voids formation at the cold end. However, when the bump height is reduced to 5.8 μm in the 3D IC samples, no significant microstructural evolution of Sn was found; instead, the dissolution of Ni under-bump metallization at hot end was observed. We propose that discrepancy between flip chip solder joints and 3D IC microbumps is mainly attributed to the effect of back stress and the presence of thicker Ni under-bump metallization in the 3D IC packaging. Moreover, the critical temperature gradient in terms of different bump heights is discussed, showing below which there will be no net effect of thermomigration of Sn.

Robust Design Analysis on Fatigue Life of Lead-Free Sn0.5Ag Solder in a Multichip Module Package

System-in-package (SiP) has become a mainstream technology in IC package industry as it provides the solutions to the growing needs of high speed functions, mobility/portability, energy efficiency, and miniaturization of electronic products. One special form of SiP is the multi-chip module (MCM) in which multiple integrated circuits (ICs), semiconductor dies or other discrete components are packaged onto a unifying substrate. Thus, the reliability of package integrity becomes one of the major reliability concerns. In the present paper, a robust design analysis on the thermo-mechanical reliability of an MCM package with flip-chip technology is demonstrated. Our results show that for the specific package, the CTE of the substrate is the most influential factor to the fatigue reliability of the package. The optimal combination of the parameters is recommended. The robust design analysis optimizes the fatigue life from 165 cycles to 1080 cycles which is a 554.5% gain on the fatigue life.

3D Integration of System-in-Package (SiP): Toward SiP-Interposer-SiP for High-End Electronics

The demand for high-performance, lightweight, portable computing power is driving the industry toward 3D integration to meet the demands of higher functionality in ever smaller packages. To accomplish this, new packaging needs to be able to integrate multiple substrates, multiple dies with greater function, higher I/O counts, smaller pitches, and greater heat densities, while being pushed into smaller and smaller footprints. The approaches explored in this paper include eliminating active chip packages by directly attaching the chip to the System-in-Package (SiP) with flip chip technology. Additionally, the area devoted to passive components can be greatly reduced by embedding many of the capacitors and resistors. In some instances, the connector systems that were consuming large amounts of space in the traditional Printed Wiring Board (PWB) assembly can be reduced with a small pitch connector system. This PWB assembly can then be transformed into a much smaller SiP with the full surface area on both sides of the package effectively utilized by active and passive components. The miniaturized SiP with its reduced package size and demand for passives requires a high wireability package with embedded passives and excellent communication from top to bottom. In the present study, we also report novel 3D “Package Interposer Package” (PIP) solution for combining multiple SiP substrates into a single package. A variety of interposer structures were used to fabricate SiP-Interposer-SiP modules. Electrical connections were formed during reflow using a tin-lead eutectic solder paste. Interconnection among substrates (packages) in the stack was achieved using interposers. Plated through holes in the interposers, formed by laser or mechanical drilling and having diameters ranging from 50 m to 250 m, were filled with an electrically conductive adhesive and cured. The adhesive-filled and cured interposers were reflowed with circuitized substrates to produce a PIP structure. In summary, the present work describes an integrated approach to develop 3D PIP solutions on various SiP configurations.

3D Integration of System-in-Package (SiP) Using Organic Interposer: Toward SiP-Interposer-SiP for High-End Electronics

The demand for high-performance, lightweight, portable computing power is driving the industry toward 3D integration to meet the demands of higher functionality in ever smaller packages. To accomplish this, new packaging needs to be able to integrate multiple substrates, multiple dies with greater function, higher I/O counts, smaller pitches, and greater heat densities, while being pushed into smaller and smaller footprints. The approaches explored in this paper include eliminating active chip packages by directly attaching the chip to the System-in-Package (SiP) with flip chip technology. Additionally, the area devoted to passive components can be greatly reduced by embedding many of the capacitors and resistors. In some instances, the connector systems that were consuming large amounts of space in the traditional Printed Wiring Board (PWB) assembly can be reduced with a small pitch connector system. This PWB assembly can then be transformed into a much smaller SiP with the full surface area on both sides of the package effectively utilized by active and passive components. The miniaturized SiP with its reduced package size and embedded passives provides a high wireability package with excellent communication from top to bottom. In the present study, we also report a novel 3D “Package-Interposer-Package” (PIP) solution for combining multiple SiP substrates into a single package. A variety of interposer structures were used to fabricate SiP-Interposer-SiP modules. Electrical connections were formed during reflow using a tin-lead eutectic solder paste. Interconnection among substrates (packages) in the stack was achieved using interposers. Plated through holes in the interposers, formed by laser or mechanical drilling and having diameters ranging from 50 μm to 250 μm, were filled with an electrically conductive adhesive and cured. The adhesive-filled and cured interposers were reflowed with circuitized substrates to produce a PIP structure. In summary, the present work describes an integrated approach to develop 3D PIP solutions incorporating various SiP configurations.

Micro-tube insertion into aluminum pads: Simulation and experimental validations

Following the trend towards more densely integrated electronic devices; new flip-chip technologies are developed to address very fine pitch interconnection. Among them, it was demonstrated that the hybridization technique based on insertion of gold coated micro-tubes into aluminum pads (Al-0.5Cu) has the capability for a 10 μm bonding pitch and the advantage of a room temperature assembly process [1, 2] . In this study, we propose to thoroughly study the electro-mechanical behavior of the micro-tube inserted into an aluminum pad. A finite element model has been used to simulate the micro-tube insertion into an aluminum pad. This numerical model deals with critical issues such as contacts, large deformations and remeshing. It was used to predict the main process parameter: the minimum load required for the micro-tube insertion into the pad. On one hand, the load should be high enough to fracture the native alumina layer during insertion and to achieve an appropriate electrical contact. On the other hand it must be low enough to prevent over-stress and deterioration of the tube and the underneath technology. The predicted load is then used in an experimental setting where the single micro-tube insertion into pads is conducted using a nano-indenter. The modified nano-indenter allows in-situ electrical measurements. The simulated load is confirmed and SEM inspections of the deformed pad are in accordance with the predicted shape. This load is shown to be influenced by the loading rate and the alignment between the micro-tubes and pads. A full understanding of the electromechanical insertion behavior is achieved thanks to these experimental setup and the simulation. These results are generalized to assemble an array of over 100 000 micro-tubes into an array of pads using a pick and place equipment. The D2W bonding process has been optimized in order to reach a 100% yield of interconnection and a high mechanical strength. Electrical measurements show that these assemblies exhibit an electrical resistance lower than 300mΩ.

Comprehensive Thermomechanical Analyses and Validations for Various Cu Column Bumps in fcFBGA

Since the employment of copper (Cu) column bump (with lead-free solder cap) interconnect offers flexibility in the aspect ratio, increases the I/O density, and provides the characteristic of fine-pitch bumps in flip-chip technology (less than 150 μm bump pitch), a significant amount of research on Cu column bumps in flip-chip packages has been carried out in recent years. For the implementations of Cu column bumps, the architectures of bump-on-capture (BOC) pad with solder bump on pre-solder and bump-on-lead (BOL) with solder bump on Cu trace are usually adopted in flip-chip packages. For the purpose of realizing the mechanical behaviors for fcFBGA (flip-chip fine-pitch ball grid array) with lead-free (LF) bump, Cu column bump, and Cu column bump without (w/o) LF solder cap (Cu column w/o solder cap), this paper presents 3-D finite element analysis (FEA) and compare their warpage and stress responses. The experimental coplanarity measurements for these three types of bumps in fcFBGA are carried out to validate the FEA results. Moreover, the reliability assessment for the underfill selection is further validated with an FEA study. Through validation and simulation, it is observed that the use of an LF bump was better at preventing extreme low- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> (ELK) failure and aluminum (Al) pad/underbump metallurgy (UBM) delamination, while the use of Cu column bump with and without a solder cap can avoid pre-solder crack failure. In addition, because the packaging geometry and material always play important roles in determining mechanical behaviors, identifying the most significant factors that affect the stress and warpage responses is useful if stress and warpage reductions in fcFBGA are required. In order to gain the essential factors in fcFBGA, systematic simulation studies for LF bump, Cu column bump, and BOL are illustrated. The impact levels for the top significant factors that influence the ELK, UBM, and bump stresses as well as the warpage are obtained through systematic simulation studies. Several suggestions for reducing warpage and the critical stresses in fcFBGA with Cu column bumps are recommended. The results show that the stresses in ELK, UBM, and bump in the BOL structure are smaller than those in a BOC structure, demonstrating that the BOL structure provides a reliable fcFBGA package without any ELK damage, UBM delamination, or bump crack issues. The perpendicular BOL orientation in the corner bump area also prevents damage that can be caused by a Cu trace or LF bump. It is believed that the proposed results will provide design guidelines to enhance package reliability and reduce the package cost during the development stage.

Transferable Redistribution Layers (TRDL)

Since the early 1990's, redistribution layers (RDL) have been used to relocate and change the pattern of the bond pads on die. RDL allows legacy parts that were designed as wirebond die to be flip-chip soldered to Printed Wiring Boards (PWBs). The flip-chip soldering technology shrinks overall board size as well as shortening electrical connection lengths. Since the introduction of this technology a couple decades ago, RDL has been performed at the wafer level through a back end of line (BEOL) process performed directly on the active surface of the wafer. Transferable redistribution layers (TRDL) may become the next evolutionary step for RDL and provide a viable solution to complex RDL. The TRDL technology allows for multi-layer RDL to be transferred from a non-active surface to an active one. TRDL is particularly important for prototyping and quick-react situations. The TRDL wafers can be processed in parallel with obtaining the active components, thereby drastically reducing the time from design to completed components.

Thermal modeling approach for enhancing TCNCP process for manufacturing fine pitch copper pillar flip chip packages

Flip chip technology has traditionally been driven by electrical performance and package miniaturization, with application processors being primary drivers for devices like smart-phones and tablets. Today solder interconnect pitches, for both low-end and high-end flip chip applications, approximately range from 200μm to 90μm in area array. Advanced silicon nodes create challenges to fine pitch flip chip interconnects and corresponding substrate technology. Fine pitch (&amp;lt;60μm pitch) flip chip (FPFC) packaging is an emerging technology that meets the demand for both smaller form factors and lower cost products. Copper pillar bumps are best suited for fine pitch applications because they allow low standoff height and robust package reliability. Previous feasibility studies show that thermo-compression bonding process with non-conductive paste (NCP) is well suited for manufacturing copper pillar based FPFC packages because the NCP paste encapsulates the bumps and protects the vulnerable die interconnects. TCNCP process can be described as (1) NCP paste is pre-dispensed on a substrate (2) bumped die is picked up by the heater tool (3) proper heating profile and compression load is applied and (4) heater tool detaches and die is allowed to cool. This process requires precise control of temperature and force to get robust flip chip interconnect shape and void-free NCP coverage. TCNCP process has very small heating times usually ranging between 2 to 4 seconds per die. Within such short time, the heater temperature is quickly ramped up to 3 times its initial temperature to melt the solder at the tip of the copper bumps and cure the NCP. Small package layers make it very difficult for the heat to spread quickly. Therefore any temperature gradients within the heater are propagated into the die. Large temperature gradients within the die can potentially introduce manufacturing related challenges like solder “non-wet” and “de-wet”. In this paper these issues are briefly discussed. An experimentally validated thermal model is presented to develop an understanding of rapid heat flow patterns during a typical TCNCP process. Detailed parametric computational study is performed on different die sizes, heating temperature and time to propose a broad guideline on achieving optimal temperature distribution during the TCNCP process.

Adopt Advanced RDL Rule to Apply Flip Chip Technology for Next Generation Si Node: Feasibility Study

With Si node shrinking to 28nm technology, smaller pitch of die pads becomes available so that more IO pads can be layed out. Sometimes the die requires flip chip packaging because of either functionality and performance requirement or cost effectiveness. This paper proposed an advanced RDL solution for a tigher pitch die. A local 10/10um L/S PBO RDL rule is applied to route a die that has three rows staggered 40/80um pitch pads into an area type die, and thermal compression method is used to assembly the chip with flip chip process. Initial construction analysis shows that this is a viable solution.

Mechanical assessment of an anisotropic conductive adhesive joint of a direct access sensor on a flexible substrate for a swallowable capsule application

Sensor interconnection achieved with Flip Chip (FC) technology and most particularly with Anisotropic Conductive Adhesive (ACA) is a very attractive technique, in achieving a Direct Access Sensor (DAS), in a swallowable diagnostic sensing capsule. This paper describes the work carried out to mechanically characterise the ACA joints when they are inserted in the capsule to determine the smallest capsule diameter that could be used without imparting excessive stress on the interconnect in the DAS integration process for a specific substrate and chip design. Three point inward bending was used to study the effect of the mechanical loading on the joints during the insertion process. The results showed that the insertion force linearly increased and leveled off at a, low friction, constant value. The spring constant of the linear region in a 23mm was 0.2729N/mm and increased to 1.5N/mm for the 15mm diameter hole. It showed that the spring constant decreased linearly as the diameter increased, signifying that for the same distance, less force will be required in a larger diameter hole than in the small diameter holes. During insertion the stress in the assembly, was higher towards the centre of the chip and the window than at the edge of the chip and the ACA fillet. This was characterised by it exhibiting lower voltage values measured in the partial daisy chains that were close to the window rather than the ones that were situated away from the window. The insertion test suggested that the 23mm diameter hole would be the smallest suitable hole for insertion of this assembly. Failure analysis revealed that the depression and the wide crack close to the window imply that the stress was high in this region. The cross sectional analysis showed that failure occurred within silicon/silicon chip pad and that the ACA contacts form a strong joint and was able to withstand the insertion force required to secure the ACA sensor in place before encapsulation.

Reliability estimation and failure mode prediction for 3D chip stacking package with the application of wafer-level underfill

With the impressive size shrinkage of advanced transistors and Cu/low-k interconnect systems, the introduction of through-silicon via integrated with three-dimensional (3D) chip-stacking approaches has become one of the major packaging technologies to meet the desired requirements of multifunctionality. The use of microbump (@m-bump) interconnected silicon chips to ensure the reliability of the interconnections is regarded as a critical issue that must be resolved. In this research, wafer-level underfill (WLUF) joined with flip-chip technology are proposed, and a nonlinear finite element analysis, combined with a process-oriented simulation technique, is used to investigate the packaging assembly effect of the WLUF thermal-compressive process. The stress predictions during the temperature cycling test is also systematically explored. The proposed simulation methodology is successfully validated through comparison with experimental data. The analytical results indicate that both the assembly and thermomechanical reliabilities of @m-bumps are determined by the arrangement of the @m-bump arrays. Consequently, the optimal designs of @m-bump layouts within the chips must be seriously considered, given that silicon chips thinner than 100@mm are assembled in 3D advanced packages.

Using BP network for ultrasonic inspection of flip chip solder joints

Flip-chip technology has been used extensively in microelectronic packaging, where defect inspection for solder joints plays an extremely important role. In this paper, ultrasonic inspection, one of the non-destructive methods, was used for inspection of flip chip solder joints. The image of the flip chip was captured by scanning acoustic microscope and segmented based on the flip chip structure information. Then a back-propagation network was adopted, and the geometric features extracted from the image were fed to the network for classification and recognition. The results demonstrate the high recognition rate and feasibility of the approach. Therefore, this approach has high potentiality for solder joint defect inspection in flip chip packaging.

Side Wall Wetting Induced Void Formation due to Small Solder Volume in Microbumps of Ni/SnAg/Ni upon Reflow

For high-density packaging in microelectronic industry, the three dimensional integrated circuits (3D IC) by vertically stacked silicon chips is expected to achieve higher performance than the conventional flip-chip technology. This is because in order to accomplish the multi-functional requirements for future generation electronics, interconnections with high input/output counts and fine pitch are needed. Therefore, fine pitch interconnections with through-siliconvias (TSVs) of Cu vias for 3D IC of Si chips has been developed recently. 1 Microbump technology is required to join the vias between Si chips. Lead-free solder bumps about 10 μ mi n height and in diameter were adopted in microbumps. 2 In contrast with conventional