Flip Chip Technology Research Articles

A High Temperature SOI-CMOS Chipset Focusing Sensor Electronics for Operating Temperatures up to 300°C

Abstract Sensors are the key elements for capturing environmental properties and are increasingly important in the industry for the intelligent control of industrial processes. While in many everyday objects highly integrated sensor systems are already state of the art, the situation in an industrial environment is clearly different. Frequently, the use of sensor systems is impossible, because the extreme ambient conditions of industrial processes like high operating temperatures or strong mechanical load do not allow the reliable operation of sensitive electronic components. Fraunhofer is running the Lighthouse Project “eHarsh” to overcome this hurdle. In the course of the project, an integrated sensor readout electronic has been realized based on a set of three chips. A dedicated sensor fron-tend provides the analog sensor interface for resistive sensors typically arranged in a Wheatstone configuration. Furthermore, the chipset includes a 32-bit microcontroller for signal conditioning and sensor control. Finally, it comprises an interface chip including a bus transceiver and voltage regulators. The chipset has been realized in a high-temperature 0.35-micron SOI-CMOS technology focusing operating temperatures up to 300°C. The chipset is assembled on a multilayer ceramic low-temperature cofired ceramics (LTCC) board using flip chip technology. The ceramic board consists of four layers with a total thickness of approximately 0.9 mm. The internal wiring is based on silver paste while the external contacts were alternatively manufactured in silver (sintering/soldering) or in gold alloys (wire bonding). As an interconnection technology, silver sintering has been applied. It has already been shown that a significant increase in lifetime can be reached by using silver sintering for die attach applications. Using silver sintering for flip chip technology is a new and challenging approach. By adjusting the process parameter geared to the chipset design and the design of the ceramic board high-quality flip chip interconnects can be generated.

Hybrid integration methodology for quantum cascade lasers with germanium waveguides in mid-IR

Mid-infrared quantum cascade lasers (QCLs) operating around 5.7 μm have been integrated with germanium waveguides on silicon substrates. QCL bars have been designed and fabricated at the University of Sheffield for the purpose of integration. This hybrid approach uses flip-chip technology that has been successfully transferred from a silicon-on-oxide (SOI) platform working at communication wavelengths, demonstrating the flexibility of this approach. Integration challenges are introduced, and solutions discussed, leading to the next iteration of design presented here.

Vacuum-gap transmon qubits realized using flip-chip technology

Significant progress has been made in building large-scale superconducting quantum processors based on flip-chip technology. In this work, we use flip-chip technology to realize a modified transmon qubit, denoted as the “flipmon,” whose large shunt capacitor is replaced by a vacuum-gap parallel plate capacitor. We place one of the qubit pads and a single Josephson junction on the bottom chip and the other pad on the top chip, which is galvanically connected with the junction through an indium bump. The electric field energy participation ratio can arrive at nearly 53% in air when the vacuum-gap is about 5 μm, thus potentially leading to a lower dielectric loss. The coherence times of the flipmons are obtained in the range of 30–60 μs, which are comparable with that of conventional transmons with similar fabrication processes. The electric field simulation indicates that the metal-air interface's energy participation ratio increases significantly and may dominate the flipmon's decoherence. This suggests that more careful surface treatment needs to be considered. No evidence shows that the indium bumps inside the flipmons cause significant decoherence. With well-designed geometry and good surface treatment, the coherence of the flipmons can be further improved.

Using convolutional neural network for intelligent SAM inspection of flip chips

The flip-chip (FC) technology is widely used in microelectronic packaging. As the dimensions and pitch of the chip solder bumps are getting smaller, defect inspection becomes increasingly challenging. In this paper, scanning acoustic microscopy (SAM) was used for the non-destructive inspection of FC packages. However, the detection accuracy may be limited by a low resolution of the SAM image. Therefore, the image super-resolution (SR) method was employed to enhance the SAM image quality. The modified very-deep SR (VDSR) algorithm, based on a convolutional neural network (CNN), was investigated to reconstruct high resolution acoustic micrographs. In addition, a CNN-based classification model was designed for the classification of the solder joints. The results obtained in the present study demonstrate that the improved VDSR combined with the CNN classification model provides excellent performance for improving the SAM detection accuracy of the inspection of flip chip packages.

Design and Switching Characteristics of Flip-Chip GaN Half-Bridge Modules Integrated with Drivers

Half-bridge modules with integrated GaN high electron mobility transistors (HEMTs) and driver dies were designed and fabricated in this research. Our design uses flip-chip technology for fabrication, instead of more generally applied wire bonding, to reduce parasitic inductance in both the driver-gate and drain-source loops. Modules were prepared using both methods and the double-pulse test was applied to evaluate and compare their switching characteristics. The gate voltage (Vgs) waveform of the flip-chip module showed no overshoot during the turn-on period, and a small oscillation during the turn-off period. The probabilities of gate damage and false turn-on were greatly reduced. The inductance in the drain-source loop of the module was measured to be 3.4 nH. The rise and fall times of the drain voltage (Vds) were 12.9 and 5.8 ns, respectively, with an overshoot of only 4.8 V during the turn-off period under Vdc = 100 V. These results indicate that the use of flip-chip technology along with the integration of GaN HEMTs with driver dies can effectively reduce the parasitic inductance and improve the switching performance of GaN half-bridge modules compared to wire bonding.

Monolithic Thin Film Red LED Active-Matrix Micro-Display by Flip-Chip Technology

A monolithic thin film red light emitting diode (LED) active-matrix (AM) micro-display driven by a complementary metal-oxide semiconductor (CMOS) driver is demonstrated. The resolution of the micro-display is 64×36, with a 40 μm ×40 μm pixel pitch. Starting from AlGaInP epi-layers grown on GaAs substrates, the monolithic red LED array was fabricated and then integrated with the AM driver using Au/In flip-chip bonding technology. After removal of the GaAs substrate, a crack-free thin film micro-display was realized with a high pixel yield. The thin film red LED AM micro-display delivers a luminance of 2.35×10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sup> cd/m <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> at full-load conditions and can render images with 4-bit grayscale. This work not only provides a manufacturing-friendly approach for monolithic thin film red LED micro-displays, but also brings the possibility of hybrid integration with blue/green LEDs to achieve full-color LED micro-displays.

A High Temperature SOI-CMOS Chipset Focusing Sensor Electronics for Operating Temperatures up to 300 °C

Abstract Sensors are key elements for capturing environmental properties and are increasingly important in the industry for the intelligent control of industrial processes. While in many everyday objects highly integrated sensor systems are already state of the art, the situation in an industrial environment is clearly different. Frequently the use of sensor systems is impossible, because the extreme ambient conditions of industrial processes like high operating temperatures or strong mechanical load do not allow a reliable operation of sensitive electronic components. Fraunhofer is running the Lighthouse Project ‘eHarsh’ to overcome this hurdle. In the course of the project an integrated sensor readout electronic has been realized based on a set of three chips. A dedicated sensor frontend provides the analog sensor interface for resistive sensors typically arranged in a Wheatstone configuration. Furthermore, the chipset includes a 32-bit microcontroller for signal conditioning and sensor control. Finally, it comprises an interface chip including a bus transceiver and voltage regulators. The chipset has been realized in a high temperature 0.35 micron SOI-CMOS technology focusing operating temperatures up to 300 °C. The chipset is assembled on a multilayer ceramic LTCC-board using flip chip technology. The ceramic board consists of 4 layers with a total thickness of approx. 0.9 mm. The internal wiring is based on silver paste while external contacts were alternatively manufactured in silver (sintering/soldering) or in gold-alloys (wire bonding). As interconnection technology, silver sintering has been applied. It has already been shown that a significant increase in lifetime can be reached by using silver sintering for die attach applications. Using silver sintering for flip chip technology is a new and challenging approach. By adjusting the process parameter geared to the chipset design and the design of the ceramic board high quality flip chip interconnects can be generated.

Effects of cooling rate and joint size on Sn grain features in Cu/Sn–3.5Ag/Cu solder joints

In Sn-based micro solder joints for fine pitch flip chip or 3D packaging technologies, the number of Sn grains is always limited and sometimes only one Sn grain exists in a joint, which inevitably causes anisotropy in the performance and reliability of micro interconnection. It is known that the parameters of solder joint structure and reflow process, especially cooling stage, have a great significance for regulating the features of Sn grains after soldering. Hence, in the present paper, the Sn grain features of Cu/Sn–3.5Ag/Cu solder joints with different joint sizes (300 μm, 100 μm and 50 μm) solidified under different cooling rates (1.5 °C/s, 0.5 °C/s and 0.1 °C/s) were studied. Generally, the number of Sn grains decreased as the joint size decreased. When the joint size was 50 μm, the solder joints tended to contain only one or two Sn grains irrespective of the cooling rate. Furthermore, cooling rates greatly affected the number and orientation of Sn grains as well as the growth of large Ag3Sn intermetallic plates to varying degrees. The formation of Sn grains and Ag3Sn plates was discussed from the viewpoint of nucleation under different conditions.

A Highly Efficient Linear Multimode Multiband Class-J Power Amplifier Utilizing GaAs HBT for Handset Modules

This article presents the design techniques for a multimode multiband (MMMB) linear RF power amplifier (PA) with a high efficiency, suitable for wireless handset multichip modules. The PA operates with high efficiency at the saturated output power and maintains high linearity with an enhanced efficiency at the back-off power. It is, thus, able to operate in multimodes (saturated/linear) and covers multibands (814-915 MHz; bands: 5/8/18/19/20/26) without reconfiguration, representing a novel solution for the converged PA module architecture to reduce the number of PAs within the handset. A new technique to the handset industry, class-J, is adopted to improve the efficiency while maintaining the linearity. To the best of our knowledge, this work provides the first implementation of the class-J using the GaAs heterojunction bipolar transistor (HBT) technology in the multichip PA modules. The utilization of the GaAs HBT adds more degrees of freedom to enhance the linearity. A PA module, consisting of a GaAs HBT die mounted on a four-layer laminate, is designed. The die is fabricated using the flip-chip technology. The output matching network and the control/bias network are fabricated on the laminate using the printed inductors and the surface-mount device (SMD) capacitors. The results validate the design techniques, showing 2G power added efficiency (PAE) 62%, 2.5G error vector magnitude (EVM) ≤ 3%, and 3G adjacent channel leakage ratio (ACLR) of 5MHz ≤ -35 dBc. The design achieves a higher PAE than other reported reconfigurable and complex MMMB PAs, with comparable linearity.

Hybrid Dickson Switched-Capacitor Converter With Wide Conversion Ratio in 65-nm CMOS

Hybrid switched-capacitor (SC) converters have shown great promise in achieving high efficiency and power density for dc–dc conversion. By combining an SC stage with an inductor filter stage, benefits from both approaches can be realized. In this work, a hybrid Dickson SC converter with a 4:1 native conversion ratio and regulated output voltage range of 0.3–0.9 V from a 3.4 to 4.2-V lithium-ion battery and the effective switching frequency of 1 MHz was implemented in 65-nm bulk CMOS process. The converter achieves maximum output current of 1.5 A, the power density of 330 mW/mm2, and a peak efficiency of 92.6%. The converter is packaged using flip-chip technology with passive devices co-packaged through a high-density interposer to minimize the packaging parasitics and volume. A segmented gate driver is used to enhance the converter efficiency and reliability by maintaining low-voltage ringing across the power switches. The converter is integrated with closed-loop output voltage regulation, dead-time control, and active capacitor–voltage balancing to maximize the active and passive device utilizations.

2 $\times$ 64-Element Dual-Polarized Dual-Beam Single-Aperture 28-GHz Phased Array With 2 $\times$ 30 Gb/s Links for 5G Polarization MIMO

This article presents a 5G 28-32 GHz 2 × 64-element dual-polarized (DP) dual-beam transmit/receive (TRX) phased array. The array is based on a SiGe 2 × 4 TRX dual-beamformer chip with 6 bits of phase and 25 dB of gain control. The chip delivers 11-12 dBm/channel in the transmit-mode and has a noise figure (NF) of 4.8 dB in the receive-mode. Sixteen chips are employed for the construction of a low-cost printed circuit board (PCB) based 2 × 64-element dual-beam array using flip-chip technology. The phased-array has two 1:16 dual Wilkinson networks and microstrip antennas with rotated feeds for cross-polarization cancellation. The array demonstrates a measured effective isotropic radiated power (EIRP) at Psat of 52 dBm for each beam and is capable of scanning ±50° in azimuth and ±25° in elevation with >28-dB cross-polarization rejection. Simultaneous dual-beam operation is demonstrated with near-ideal patterns for each beam. The array demonstrates independent simultaneously transmitted 2 × 16-quadrature amplitude modulation (QAM) and 2 × 64QAM data streams delivering an aggregate maximum data rate of 2 × 20 and 2 × 30 Gb/s, respectively. Also, measurements done over all scan angles at an EIRP of 41 dBm per polarization and 64-QAM waveforms show a data rate of 2 × 4.8 Gb/s with an EVM ≤ -25 dB. To our knowledge, this is the first demonstration of a dual-polarized dual-beam phased array for 5G polarization-based multiple-input-multiple-output (MIMO) systems with 60-Gb/s maximum data rates.

Ultrasonic signal denoising technology based on SMP algorithm

Flip chip technology has been rapidly developed and widely used in the field of microelectronic packaging, and defect detection has received increasing attention. The ultrasonic detection method is used to detect the defect information of the packaged chip. However, the ultrasonic signal obtained during the detection process is disturbed by noise, which seriously affects the true information of the defect signal. For this problem, the matching matching pursuit (SMP) algorithm is used in combination with Gabor. The atomic library realizes adaptive matching of noisy ultrasonic signals. The linear combination of selected atoms is used to represent the denoised signals to achieve the denoising effect of noisy ultrasonic signals. The denoising effect of the SMP algorithm in the experiment is compared with the MP algorithm, and the results show that the denoising effect of the SMP algorithm is better.

Electrical testing of small-series multi-chip microcircuit samples combining Wire Bond and Flip-Chip technologies

The paper provides a technical solution and methodology for conducting automated electrical and functional testing of small series samples of multi-chip assemblies. The results of multi-chip assembly samples testing combining Wire Bond and Flip-Chip technologies are presented. Based on the test results, defects that occur during the packaging process are localized and the assembly stages at which these defects occur are determined.

Simulation Research on Sparse Reconstruction for Defect Signals of Flip Chip Based on High-Frequency Ultrasound

Flip chip technology has been widely used in various fields. As the density of the solder balls in flip chip technology is increasing, the pitch among solder balls is narrowing, and the size effect is more significant. Therefore, the micro defects of the solder balls are more difficult to detect. In order to ensure the reliability of the flip chip, it is very important to detect and evaluate the micro defects of solder balls. High-frequency ultrasonic testing technology is an effective micro-defect detection method. In this paper, the interaction mechanism between high-frequency ultrasonic pulse and micro defects is analyzed by finite element simulation. A transient simulation model for the whole process of ultrasonic scanning of micro defects is established to simulate scanning in acoustic microscopy imaging. The acoustic propagation path map is obtained for analyzing acoustic energy transmission during detection, and the edge blurring effect in micro-defect imaging detection is clarified. The processing method of the time-domain signal and cross-section image signal of micro defects based on sparse reconstruction is studied, which can effectively improve the accuracy of detection and the signal-to-noise ratio.

Effects of Cooling Rate and Joint Size on Sn Grain Features in Cu/Sn-3.5ag/Cu Solder Joints

In Sn-based micro solder joint s for fine pitch flip chip or 3D packaging technologies , the number of Sn grains is always limited and sometimes only one Sn grain exists in a joint, which inevitably causes anisotropy in the performance of micro interconnection. It is known that the parameters and reliability of solder joint structure and reflow process, especially cooling stage, have a great significance for regulating the features of Sn grain s after soldering. Hence, in the present paper, the Sn grain features of Cu/Sn-3.5Ag/Cu solder joints with different joint size s (300 μm, 100 μm and 50 μm) solidified under different cooling rate s (1.5 °C /s, 0.5 °C /s and 0.1 °C /s) were studied. Generally, the number of Sn grains decrease d as the joint size decrease d . When the joint size was 50 μm, the solder joints tended to contain only one or two Sn grains irrespective of the cooling rate. Furthermore, cooling rates greatly affected the number and orientation of Sn grains as well as the growth of large Ag3Sn intermetallic plates to varying degrees. The formation of Sn grains and Ag 3 Sn plates was discussed from the viewpoint of nucleation under different conditions.

Manufacturing processes for fabrication of flip-chip micro-bumps used in microelectronic packaging: An overview

Electronic packaging is the methodology for connecting and interfacing the chip technology with a system and the physical world. The objective of packaging is to ensure that the devices and interconnections are packaged efficiently and reliably. Chip–package interconnection technologies currently used in the semiconductor industry include wire bonding, tape automated bonding and flip-chip solder bump connection. Among these interconnection techniques, the flip-chip bumping technology is commonly used in advanced electronic packages since this interconnection is an area array configuration so that the entire surface of the chip can be covered with bumps for the highest possible input/output (I/O) counts. The present article reviews the manufacturing processes for the fabrication of flip-chip bumps for chip–package interconnection. Various solder bumping technologies used in high-volume production include evaporation, solder paste screening and electroplating. Evaporation process produces highly reliable bumps, but it is extremely expensive and is limited to lead or lead-rich solders. Solder paste screening is cost-effective, but issues related to excessive void formation limits the process to low-end products. On the other hand, electrochemical fabrication of flip-chip bumps is an extremely selective and efficient process, which is extendible to finer pitch, larger wafers and a variety of solder compositions, including lead-free alloys. Electrochemically fabricated copper pillar bumps offer fine pitch capabilities with excellent electromigration performance. Due to these virtues, the copper pillar bumping technology is emerging as a lead-free bumping technology option for high-performance electronic packaging.

Modeling the temperature distribution of multi-chip integrated circuits combining Wire-Bond and Flip-Chip technologies

On the basis of finite-element computer modeling, the temperature distribution of a multi-chip integrated circuit was calculated in System on Package configuration, combining Wire-Bond and Flip-Chip technologies. Technical recommendations are suggested for choosing a compound, taking into account the continuous layer of the compound separating the active elements and the heat sink.

Packaging of Ultrathin Flexible Magnetic Field Sensors With Polyimide Interposer and Integration in an Active Magnetic Bearing

Ultrathin sensors enable various scopes for measuring signals in restricted geometries. One example is the use of magnetic field sensors in active magnetic bearings (AMBs). Here, the thin sensor will allow measuring the magnetic flux directly in the air gap between the rotor and the stator of the AMB, which allows controlling the AMB faster and more precisely. This also results in a higher stiffness of the AMB. Therefore, the sensor has to be thinner than $150~\mu \text{m}$ . In this article, previous experiences with polyimide- and silicon-based Hall sensors which rely on thin bismuth films were used to realize a reliable sensor with suitable interconnection technologies. Especially the adhesive flip-chip technology, which was used with silicon interposers, has to be adapted and optimized for the packaging of polyimide-based sensors. The technologies and the materials were optimized for this approach with a special test design setup. Afterward, the working sensor systems were manufactured. These sensors show very promising results and could be successfully integrated into an AMB setup for preliminary tests.

Flip-Chip Flux Evolution

Abstract Flip-chip assembly accounts for more than 80% of the advanced packaging technology platform, compared to fan-in, fan-out, embedded die, and through silicon via (TSV). Flip-chip interconnect remains a critical assembly process for large die used in artificial intelligence processors; thin die that warps at elevated temperatures; heterogeneous integration in SiP applications; flip-chip on leadframe; and MicroLED die usage. This paper will first outline trends in evolving flip-chip and direct chip placement (DCP) technology, then will examine the changing nature of the solder bump, the interconnect itself, and the substrate. Many variables of the flip-chip assembly process will be discussed, including standard solder bumps to micro Cu-pillar bumps with different alloys; different pad surface finishes of Cu OSP, NiAu, and solder on pad (SOP); and from regular pads on substrates to bond-on-trace applications. A major focus will be on flip-chip assembly methods, from old C4 conventional reflow processing to thermocompression bonding (TCB), and the latest laser assisted bonding (LAB) technology, with an emphasis on how the usage of different technologies necessitates different assembly materials, especially fluxes. Flip-chip fluxes such as the commonly used water-washable flux, the standard no-clean flux, and the ultra-low residue flux, and how these fluxes react to different processing methods, will be an area of discussion. Finally, the paper will examine the need for increased reliability as the technology inevitably moves into the high-volume, zero-defect arena of automotive electronics.

Embrace the Journey and Harness the Power of Your Network: A Woman’s Perspective

Electrochemistry and electrochemical engineering have evolved into important disciplines enabling unprecedented progress in micro and nanoelectronics. Because of the complexity of electronic devices, the path to innovation is very complex. It requires a thorough understanding of materials and device characteristics, integration of materials and processes and process scale up, control based on sound electrochemical engineering practices and a multidisciplinary, diverse team. The electrochemical fabrication of flip-chip solder technology is an extremely selective and efficient process which is extendible to larger wafer sizes, to finer dimensions and to higher C4 density. Focus was on the development of a technology was based on additive and subtractive thin film processing. Modeling, experimental matrices, process control and equipment were developed to enable great manufacturability and scalability of the flip-chip process. CIGS is one the most promising thin film solar materials and more mature for scale-up. For the electrodeposition of CIGS we adopted a thin film deposition approach of Cu/In/Ga thin films. Key challenges are the deposition of uniform nanometer scale thin films on meter large resistive substrates, controlling nucleation and growth and tailoring the microstructure of the thin film in order to control the composition and microstructure of the final CIGS chalcopyrite layer. Scaling-up of the technology re-used concepts from the paddle cell developed for the magnetic recording and C4 processes. In Healthcare, medical devices will provide value by offering cognitive real-time analytics of biological data at the point of care and of sensing. Real-time analytics will require continuous streaming of large data sets. Neuromorphic chips will play a key role in connecting bio-sensors directly with deep-learning technology creating a closed-loop interface back to the user. By linking chip technology to advances in electrochemical bio-sensing and deep-learning, we aim to create advances in the fields of mental health, neurology and neuroimmunology. Successfully executing on all this research required multi-disciplinary diversified teams that work very closely for years in order to innovate. In the end, people who have worked together on a multi-year project become collaborators for life. My key strength is perseverance and flexibility and I am on a mission to create technologies that will impact society. This is the driving force for waking up every morning and doing work. How do I leverage my strength to have an impact and to innovate over the years? I use my networks. Using my networks to build a team of "trusted" advisors, mentees, mentors and colleagues who can complement my strengths and who support me in any new research direction or implementation of a new idea. I surround myself with colleagues that I trust and who trust me. Trust is something that one earns as one selflessly gives back to the network. In time, colleagues from the network give back, compliment my strengths, cover my weaknesses and help me accomplish my goals and passions. Furthermore, I work to develop other leaders who could succeed me in my current role. Developing others and having mentees is one of the most rewarding experiences. In the end, we all benefit from gender equality in the workplace. Companies and institutions that leverage the full talents of their workforce are more innovative and as a result have a competitive advantage and win in the marketplace. Gender equality requires societal change and it will happen if we work together supporting diversity and harnessing the power of our networks.