Reliability estimation and failure mode prediction for 3D chip stacking package with the application of wafer-level underfill

Abstract

With the impressive size shrinkage of advanced transistors and Cu/low-k interconnect systems, the introduction of through-silicon via integrated with three-dimensional (3D) chip-stacking approaches has become one of the major packaging technologies to meet the desired requirements of multifunctionality. The use of microbump (@m-bump) interconnected silicon chips to ensure the reliability of the interconnections is regarded as a critical issue that must be resolved. In this research, wafer-level underfill (WLUF) joined with flip-chip technology are proposed, and a nonlinear finite element analysis, combined with a process-oriented simulation technique, is used to investigate the packaging assembly effect of the WLUF thermal-compressive process. The stress predictions during the temperature cycling test is also systematically explored. The proposed simulation methodology is successfully validated through comparison with experimental data. The analytical results indicate that both the assembly and thermomechanical reliabilities of @m-bumps are determined by the arrangement of the @m-bump arrays. Consequently, the optimal designs of @m-bump layouts within the chips must be seriously considered, given that silicon chips thinner than 100@mm are assembled in 3D advanced packages.