Reliability enhancements of chip-on-chip package with layout designs of microbumps

Abstract

To enhance the assembly quality and mechanical reliability of microbumps during the stacking process of multiple thin chips and during temperature cycling tests, a novel wafer-level underfill (WLUF) fabrication technique has been proposed to resolve these problems. However, the occurrence of a severely warped condition or gap reduction between stacked chips has been observed during WLUF assembly with thermal compression. This condition prevents the objective achievement of a three-dimensional integrated circuit package. To address such an urgent issue, this study presents process-oriented stress simulation based on the finite element method to determine its root cause. Using a comparison with experimental data, results indicate that the major influential factors inducing thermomechanical stress within a chip-on-chip package are caused by a large temperature difference in the mechanical properties and process of WLUF. The use of WLUF with a low coefficient of thermal expansion and a low Young’s modulus is beneficial because it reduces plastic strain of critical microbumps. The use of layout designs for microbump arrays with arranged dummy joints significantly improves the co-planarity of the whole packaging structure. The simulated predictions indicate that when more than three dummy joints are placed near the outermost microbump, the warping variation between the packaging center and the chip edge at the top surface of a package under a load of a 2.0kg bonding force would be <70nm. Simultaneously, a minimum equivalent plastic strain of ∼0.87% on the critical microbump is obtained during a thermal cycling load.