Abstract
A three-dimensional integrated circuit (3D-IC) structure with a significant scale mismatch causes difficulty in analytic model construction. This paper proposes a simulation technique to introduce an equivalent material composed of microbumps and their surrounding wafer level underfill (WLUF). The mechanical properties of this equivalent material, including Young’s modulus (E), Poisson’s ratio, shear modulus, and coefficient of thermal expansion (CTE), are directly obtained by applying either a tensile load or a constant displacement, and by increasing the temperature during simulations, respectively. Analytic results indicate that at least eight microbumps at the outermost region of the chip stacking structure need to be considered as an accurate stress/strain contour in the concerned region. In addition, a factorial experimental design with analysis of variance is proposed to optimize chip stacking structure reliability with four factors: chip thickness, substrate thickness, CTE, and E-value. Analytic results show that the most significant factor is CTE of WLUF. This factor affects microbump reliability and structural warpage under a temperature cycling load and high-temperature bonding process. WLUF with low CTE and high E-value are recommended to enhance the assembly reliability of the 3D-IC architecture.
Highlights
Chip stacking assembly in three-dimensional integrated circuits (3D-ICs) packaging architecture, assisted by through-silicon via (TSV) and microbumps, has become a mainstream approach.The requirements for this process, which resulted from the development of the Internet of Things, have attracted attention. 3D-IC technology is a promising solution to integrate heterogeneous functions with high interrelated density [1]
Dissimilar to the traditional 2.5D/3D ICs packaging structures, it should be noted that the metal-filled TSV arrays do not need to be taken into account because the major purpose of the present vehicle developed by ourselves is to meet the requirements of demonstrating the material compositions, electrical characteristics, and reliability of micro-joints after packaging assembly
Based on the validated finite element analysis (FEA) of the packaging model combined with equivalent materials of microbump extracted through previous analysis four factors, namely, chip thickness, substrate thickness, coefficient of thermal extension (CTE), and E-value of wafer level underfill (WLUF), are used for three-level factorial designs and subsequent analysis of variance (ANOVA)
Summary
Chip stacking assembly in three-dimensional integrated circuits (3D-ICs) packaging architecture, assisted by through-silicon via (TSV) and microbumps, has become a mainstream approach. The requirements for this process, which resulted from the development of the Internet of Things, have attracted attention. This paper investigates and extracts the temperature-dependent stress-strain curves and equivalent mechanical properties for the microbump array of chip stacking assemblies. Dissimilar to the traditional 2.5D/3D ICs packaging structures, it should be noted that the metal-filled TSV arrays do not need to be taken into account because the major purpose of the present vehicle developed by ourselves is to meet the requirements of demonstrating the material compositions, electrical characteristics, and reliability of micro-joints after packaging assembly
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