Flash Analog-to-digital Converter Research Articles

Charge-Domain Static Random Access Memory-Based In-Memory Computing with Low-Cost Multiply-and-Accumulate Operation and Energy-Efficient 7-Bit Hybrid Analog-to-Digital Converter

This study presents a charge-domain SRAM-based in-memory computing (IMC) architecture. The multiply-and-accumulate (MAC) operation in the IMC structure is divided into current- and charge-domain methods. Current-domain IMC has high-power consumption and poor linearity. Charge-domain IMC has reduced variability compared with current-domain IMCs, achieving higher linearity and enabling energy-efficient operation with fewer dynamic current paths. The proposed IMC structure uses a 9T1C bitcell considering the trade-off between the bitcell area and the threshold voltage drop by an NMOS access transistor. We propose an energy-efficient summation mechanism for 4-bit weight rows to perform energy-efficient MAC operations. The generated MAC value is finally returned as a digital value through an analog-to-digital converter (ADC), whose performance is one of the critical components in the overall system. The proposed flash-successive approximation register (SAR) ADC is designed by combining the advantages of flash ADC and SAR ADC and outputs digital values at approximately half the cycle of SAR ADC. The proposed charge-domain IMC is designed and simulated in a 65 nm CMOS process. It achieves 102.4 GOPS throughput and 33.6 TOPS/W energy efficiency at array size of 1 Kb.

500 MS/s 4-Bit Flash ADC with Complementary Architecture

This paper proposes a 500 MS/s 4-bit flash analog-to-digital converter (ADC) featuring a differential input voltage range of 1.2 V<sub>pp</sub> operating at a supply voltage of 1.2 V. Although the proposed circuit utilizes a conventional flash ADC structure, its track and hold circuit, driving buffer, and preamp circuits corresponding to the analog stages are designed using complementary architecture to attain a sufficient swing range even at a low supply voltage. Notably, the proposed structure satisfies the error requirements. The error source of the flash ADC, such as the comparator’s input referred offset, did not degrade its performance, while the use of a calibration circuit, characterized by power consumption and area burdens and increased complexity, could also be avoided. Therefore, the proposed flash ADC met the error requirements, such as the comparator’s input referred offset, without the need for calibration circuits. The chip, fabricated using the TSMC 65 nm process, covers an area of 1,160 × 950 μm<sup>2</sup> and consumes 78 mW of power. Furthermore, its signal-to-noise and distortion ratio and spurious-free dynamic range were measured to be 23.36 dB and 30.26 dB, respectively, at a sampling frequency of 500 MHz.

180 nm FLASH ANALOG TO DIGITAL CONVERTOR

In this paper, Threshold Inverter Quantizer (TIQ) is a novel idea which can effectively replace the reference voltage generator, resistive/capacitive voltage divider network and array of differential comparators in a conventional flash Analog to Digital Converter (ADC) by an internal reference comparator array constructed of Complementary Metal Oxide Semiconductor (CMOS) inverters. The inverter threshold voltage serving as the reference voltage, this architecture claims large improvements in terms of silicon area, power consumption and operating speed. Perturbations due to sensitivity of the inverter threshold voltage to operating temperature/process variations pose impediments in such ADC designs and strongly demand a compensation scheme to such variations. This paper presents a TIQ based flash ADC, with inverter threshold voltage compensation. In this project 5 bit flash adc using TIQ Comparator is designed and simulated using TANNER EDA in 180nm technology. Key Words: flash, adc, tiq(threshold inverter quantization)

A novel hermetic detection system of KAPAE for measuring multiphoton decays of positronium

The detection system of the Kyungpook National University Advanced Positronium Annihilation Experiment (KAPAE) has a 4π coverage with fine segmentation for measuring multi- photon decays of positronium to improve the charge (C), charge-parity (CP), and charge-parity-time reversal (CPT) violations in lepton sector as well as for studying rare decays. In addition, various exotic decays of positronium can be studied with the KAPAE detector. In the KAPAE, all aspects of the detector design, fabrication, and data analysis for physics studies related to positronium annihilation are covered. In this paper, we describe the above-mentioned first fully assembled detection system developed for KAPAE, which consists of a trigger and a gamma-ray detector. The newly proposed multi-layered trigger consists of a 22Na positronium source deposited on a plastic scintillator and a silicon photomultiplier (SiPM), and the gamma-ray detector contains an aerogel at the centre in a nitrogen environment. The gamma-ray detector minimizes pile-up events by fine segmentation of 196 Bi4Ge3O12 (BGO) crystal scintillators, whose scintillation lights from both sides are readout by the SiPM. The signals of a 392-channel SiPM are fed to a preamplifier followed by a 65 MHz flash analog-to-digital converter (FADC). In this paper, the KAPAE detector design, fabrication, and performance are presented.

Comparison of Low Power High Speed Comparator for Flash ADC

The analog to digital converter (ADC), a bridge between digital world and analog world, plays a crucial role in the modern semiconductor industry. Among different types of ADCs, the flash ADC (also known as the direct-conversion ADC) is exceedingly fast, whose high sample rate enables many large bandwidth applications, such as optical communication, radar detection. The comparator circuit is one of the critical components of flash ADC. The characteristics, like latency, gain and power consumption, of comparators determine the overall performance of flash ADCs. This paper analyzes and compares different types of comparator architecture and suggests a high-performance design for flash ADC.

Development of apparatus for mean-lifetime measurement of cosmic-ray muons using plastic scintillation detectors and FLASH-ADC/FPGA-based readout electronics

Introduction: This paper presents the development and results of an apparatus for measuring the mean lifetime of cosmic-ray muons. Methods: The apparatus uses three plastic scintillation detectors and a readout electronics system based on Flash Analog Digital Converter (Flash-ADC) and Embedded Field Programmable Gate Array (FPGA). The readout system has 8-bit resolution and a 125 Msample/sec sampling rate. The system's trigger and data collection are controlled through a computer interface based on LabVIEWTM. The readout electronics are calibrated with an accuracy of 8 nsec/TDC channel. Results: Over 6000 events were recorded during the measurements performed at ground level using aluminum as the muon stopping material, and the muon decay time spectrum was obtained and fit with a combination of two exponential components and a constant background. The mean lifetimes of negative and positive muons were determined. Conclusion: Our results indicate that the mean lifetimes of negative and positive muons in aluminum are 0.70 ± 0.24 µsec and 2.05 ± 0.16 µsec, respectively.

A 6-Bit 20 GS/s Time-Interleaved Two-Step Flash ADC in 40 nm CMOS

A 6-bit 20 GS/s 16-channel time-interleaved (TI) analog-to-digital converter (ADC) using a two-step flash ADC with a sample-and-hold (S/H) sharing technique and a gain-boosted voltage-to-time converter (VTC) is presented for high-speed wireline communication systems. By sharing one S/H between coarse and fine stages in the two-step flash ADC, the input bandwidth as well as area and power efficiency can be improved without a gain error between coarse and fine ADCs. Thanks to an eight-time interpolation using the gain-boosted VTC, the fine ADC has a small gate capacitance without a speed penalty, even in a small input voltage range. A prototype ADC implemented in a 40 nm CMOS process occupies a 0.1 mm2 active area. The measured differential non-linearity (DNL) and integral non-linearity (INL) after offset and gain calibrations were 0.45 and 0.39 least significant bit (LSB), respectively. With a 9.042 GHz input, the measured signal-to-noise and distortion ratio (SNDR) and the spurious-free dynamic range (SFDR) were 30.12 and 40.23 dB, respectively. The small input capacitance of the sub-ADC enables a power-efficient track-and-hold amplifier (THA), resulting in a power consumption of 56.2 mW under a supply voltage of 0.9 V. The prototype ADC achieves a figure of merit (FoM) of 107.4 fJ/conversion-step at 20 GS/s.

Low Area and High Bit Resolution Flash Analog to Digital Converter for Wide Band Applications: A Review

: This work reviews the design challenges of CMOS flash type Analog-to-Digital Converter (ADC) for making high bit resolution, low area, low noise, low offset, and power-efficient architecture. Low-bit resolution flash ADC architecture, high-speed applications, and wide-area parallel comparators are identified on their suitability of the design for ADCs. These are effective in the area and bit resolution. The overview includes bit resolution, area, power dissipation, bandwidth and offset noise consideration for high-speed flash ADC design. A MUX-based two-step half flash architecture is considered for applications requiring 1 GHz 16-bit resolution low area and low power consumption. An advanced comparator, MUX, a high-speed digital-to-analog converter (DAC), and MUX-based encoder are also reviewed. The design of technology-efficient ADC architecture is highly challenging for the analog designer.

A 7-Bit Two-Step Flash ADC With Sample-and-Hold Sharing Technique

A 7-bit 3 GS/s two-channel time-interleaved two-step flash analog-to-digital converter (ADC) with 7-GHz effective resolution bandwidth (ERBW) is presented. A reference-embedding flash ADC for a fine stage having only a single capacitive digital-to-analog converter improves the power efficiency and area efficiency as well as the input bandwidth. The proposed sample-and-hold sharing structure not only improves the input bandwidth by removing the effect of the input capacitance of the fine ADC (FADC) but also eliminates the gain error between the coarse ADC and the FADC. The advanced sequential slope-matching offset calibration technique in the eight-time interpolated FADC improves the gain of the voltage-to-time converter and the interpolation linearity. A prototype ADC implemented in a 40-nm CMOS process occupies 0.03 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , including offset calibration circuitry. The measured peak differential non-linearity (DNL) and integral non-linearity (INL) after calibration are 0.53 and 0.47 LSB, respectively. With a 1.49-GHz input, the measured signal-to-noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) are 39.94 and 55.78 dB, respectively. The ERBW without and with time skew calibration is 4.8 and 7 GHz, respectively. The power consumption is 6.8 mW under a supply voltage of 0.9 V, leading to a figure of merit (FoM) of 28 fJ/conversion-step at 3 GS/s.

Self-Healing of Redundant FLASH ADCs

Analog-to-digital converters (ADCs) are ubiquitous and indispensable components in an Internet of Things (IoT) world, bridging the analog to the digital, and FLASH ADCs have long been prominent in the high-performance, high-area design space. This article describes an approach to FLASH ADC that combines comparator selection for calibration with normal operation, thus saving space and increasing resilience.

A 5-GS/s 6-Bit 15.07-mW Flash ADC With Partially Active Second-Stage Comparison and 2× Time-Domain Interpolation

This article presents a 5-GS/s 6-bit flash analog-to-digital converter (ADC) in a 28-nm fully depleted silicon-on-insulator (FDSOI) CMOS process. The ADC jointly employs partially active second-stage comparison and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2\times $ </tex-math></inline-formula> time-domain latch interpolation (TDI) to reduce power consumption and avoid extensive calibrations. To enhance the conversion speed of the second-stage structure, the stringent timing constraint is resolved by a 25%–75% duty-cycle clock scheme, a 0.5-bit redundancy in the first comparison stage, and an embedded second-stage slice selection logic. The bandwidth requirements of the track-and-hold (T/H) and T/H buffer under the 25%–75% duty-cycle clock are analyzed. An on-chip successive-approximation (SA)-based comparator offset calibration scheme utilizing FDSOI back-gate bias is also developed, providing sufficient calibration range without impairing comparator speed. The measured prototype achieves a signal-to-noise and distortion ratio (SNDR) of 32.8 dB and a spurious-free dynamic range (SFDR) of 41.82 dB at Nyquist frequency while consuming 15.07 mW power, translating into a Walden figure-of-merit (FOM) of 84.5 fJ/conversion-step.

THE OUTPUT NOISE REDUCTION OF A FLASH ANALOG-DIGITAL CONVERTER

A new approach to reducing output noises in the Flash analog-digital converter (ADC) is presented. A type of ADC with the least amount of noise is Flash ADC, but it also needs to have noises as less as possible. By using this method in 32nm technology, the area of the circuit increases by 72% and the noise error decreases by 63%. This method is very preferable to use for high bit Flesh ADC circuits, as the latter have many logic cells in the Encoder. Switching inputs of those cells leads to high noises in the output.

A MODEL OF A LOW POWER ANALOG-TO-DIGITAL CONVERTER BASED ON INVERTERS

In nanometer technology, static and dynamic power consumption of integrated circuits becomes almost equivalent. The problem of energy consumption, in turn, leads to the occurrence of aging and self-heating phenomena in an integrated circuit, which are the main phenomena that undermine the reliability of modern integrated circuits. Thus, nowadays, such design models of integrated circuits are proposed, in which the elements with high power consumption miss. The resistors used in the classical model of a flash analog-todigital converter are a huge source of static power consumption. On the other hand, according to the requirements set to these resistors, they must serve as a source of reference voltages of various levels in the circuit, providing stable voltage values. However, it is known that after manufacturing there are significant deviations depending on the environmental thermal vibrations and operating frequencies of the system, therefore, these circumstances in many cases limit the use of a classical flash analog-to-digital converter. In addition to the above highlighted problems, the implementation of resistors in integrated circuits requires a large area, which is also a serious problem in the field of manufacturing modern integrated circuits. The paper proposes a new model of a flash analog-to-digital converter based on inverters with different levels of supply voltages. This converter avoids the use of resistors and comparators. The proposed model allows to receive a digital signal with an amplitude of 0.8 V using an input analog signal with an amplitude of 1.8 V. It has been designed for a 14 nm process at a temperature of 25°C. The application of the proposed method allows to reduce power consumption by 7·102 times in comparison with the classical circuit with comparators and a voltage divider.

High speed area efficient 5-bit hybrid Flash ADC using spin devices and CMOS

This paper uses current induced domain wall motion in a magnetic stripe and pre-charge sense amplifiers (PCSA) to design a  high speed  comparator of a magnetic flash ADC. Current-induced domain-wall (DW) motion is a prominent switching mechanism  promising,  high-density and high-speed circuits. Domain-wall motion in a magnetic stripe based magnetic flash ADC (Analog to Digital Converter) is area efficient and faster compared to other ADCs.  Our proposed 5-bit Flash ADC can operate at 500MS/s with power consumption of 10.5mW. The power consumption can be further reduced to 5.06mW by choosing a smaller step size of 10mV. By using MTJ and domain wall motion in a magnetic stripe with PCSA, SPICE compatible Verilog-A model and CMOS 45nm design kit, its performance such as power and delay have been simulated and compared with other ADCs.

Modeling and Design of Resistor Ladder Network for High Frequency Superconductor Flash ADC

We present in this paper the design and implementation of a multilayer 6-bit resistor ladder network capable of operating up to 50 GHz for use in superconductor flash analog to digital converters (ADCs). Implementation of such a resistor network requires the design and optimization of various resistors (25 Ohm, 37.5 Ohm, and 50 Ohm). It is important to minimize the parasitic elements (inductance and capacitance) associated with resistor layout in-order to maintain the performance of the resistor ladder network up to 50 GHz. The paper proposes the use of floating niobium layers around the resistor layer to minimize parasitic effects. The fabricated 6-bit resistor network has a size of 3.2 mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$ \times $</tex-math></inline-formula> 3.2 mm and is tested in a Lake Shore Cryogenic probe station. The measured results for the individual resistors and the overall integrated network are in agreement with the EM simulation results.

An Area-Efficient SAR ADC With Mismatch Error Shaping Technique Achieving 102-dB SFDR 90.2-dB SNDR Over 20-kHz Bandwidth

To minimize the area of analog-to-digital converters (ADCs) for multichannel applications and break the SNDR limitation caused by DAC-induced nonlinearity, a more area-efficient mismatch error shaping (MES) scheme is proposed in noise shaping (NS) successive-approximation (SAR) ADC. By employing a switched-capacitor (SC) voltage divider, the proposed method makes the flash ADC and data weighted averaging (DWA) digital circuits in the original MES method obsolete. Therefore, the complexity of the architecture is highly reduced, and the area is significantly reduced to 0.037 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . In addition, the power consumption for the MES implementation is significantly decreased by more than 7.3%. The proposed SAR ADC is fabricated in GF 40-nm CMOS technology. The measurements show that the proposed MES technique improves the SFDR from 64 to 102 dB and decreases the THD from -63.6 to -95.7 dB. The SNR and SNDR in a 20-kHz bandwidth are 91.6 and 90.2 dB, respectively. The power consumption is 383.4 μW with a 1.1-V power supply at a 16-MS/s sampling rate.

A low‐power 10‐bit CCP‐based pipelined ADC using a multi‐level variable current source MDAC and an ultra‐low‐power double‐tail dynamic latch

SummaryIn this paper, a low‐power 10‐bit 15‐MS/s opamp‐less pipelined analog‐to‐digital converter (ADC) has been proposed. The circuit is comprised of eight 1.5‐bit/stage MDACs and a 2‐bit backend flash ADC. Each 1.5‐bit/stage structure comprises a CCP‐based MDAC which uses a modified multilevel variable‐current‐source (ML‐VCS) scheme. The modified ML‐VCS CCP structure facilitates its usage in a pipeline ADC structure. Also, the proposed ML‐VCS structure improves the speed behavior as well as the power consumption of a 1.5‐bit/stage CCP‐based MDAC structure. In order to further reduce power consumption, an ultra‐low‐power low‐delay double‐tail dynamic latch has been offered which features high‐speed operation. The suggested ADC is simulated using 180‐nm scaled CMOS technology with a 2‐Vp‐p differential full‐scale input voltage. Hspice simulation results show that the ADC exhibits an SNDR of 60‐dB, an ENOB of 9.67 bits, and the FOM of 0.546 PJ/Conv.step at a Nyquist‐rate input frequency. According to the results, the proposed 10‐bit ADC consumes only 6.7‐mW under a 1.8‐V supply voltage.

A Design of 44.1 fJ/Conv-Step 12-Bit 80 ms/s Time Interleaved Hybrid Type SAR ADC With Redundancy Capacitor and On-Chip Time-Skew Calibration

A 12-bit 80 MS/s hybrid type analog-to-digital converter (ADC) for high sampling speed and low power applications is presented in this paper. It has a subranging architecture with a front end of 6-bit Flash ADC with five channels of 6-bit time interleaved synchronous Successive Approximation Register (SAR) ADC. The proposed architecture with a shared 6-bit Flash ADC and time interleaved SAR ADC provides a power and area efficient high speed ADC. The proposed Time-skew calibration is implemented to minimize the discrepancy between the output of Flash ADC and SAR ADC’s channels. To rectify the decision error of the Flash ADC and extract the time-skew information, 1-bit redundancy is included in the CDAC of the SAR conversion. The decision error between the Flash ADC and the SAR ADC is covered with designed redundancy and the mismatch between the ADCs is covered with the time-skew calibration. To reduce the offset mismatch between Flash and SAR ADC and within SAR ADCs, all comparators are calibrated to minimize their absolute offset by utilizing background offset calibration. The modified dynamic strong ARM comparator is used for flash ADC and dynamic latched comparator is used for SAR ADCs. For fine offset calibration and low power consumption, the comparator’s offset calibration circuit is implemented. To reduce the kickback noise and enhance the overall energy efficiency for fast operation of SAR ADCs, rail-to-rail dynamic latch comparator with modified adaptive power control (APC) is implemented. The proposed ADC structure has been implemented in 130 nm CMOS process. The ADC has an effective number of bit (ENOB) of 10.97 bits while consuming 7.08 mW current consumption from the 1.2 V supply voltage.

Высокоточный двухступенчатый АЦП с изменяемым диапазоном сравнения с использованием компаратора на основе защелки

Due to the technology development and decreasing supply voltages, undesirable effects on sensitive analog signals like noise, kickback are becoming more expressed. Mentioned issues are present in analog to digital converters (ADC) and design of high accuracy ADCs is becoming more complex. In this work, a circuit was proposed based on a latch comparator and comparison range shifter, which increased the accuracy of a two-step flash ADCs by excluding the chance of incorrect coarse conversion, when the input analog voltage is close to separating points of the comparison range of first stage of the ADC. The proposed circuit was constructed using an 16nm FinFET process, the simulations were done with HSpice simulator. The idea was to increase the accuracy of an already designed two-step flash ADC by adding the proposed circuit, which was done by shifting the comparison range during the coarse conversion, for the difference of input voltage and separating points not to be smaller than the offset of comparators used in ADC. It was established that the use of the proposed circuit increased the comparison time, as the sampled input analog voltage firstly should be compared with comparison range separating points, but on the other hand the ADC became more sensitive to its input change (up to 4mV offset) and was performing stable, excluding the chance of wrong coarse conversion. It has been shown that proposed architecture allows avoiding the use of low offset and high accuracy complex comparators in two-step flash ADCs, which greatly reduces the layout area.

IMPLEMENTATION OF A REDUCED COMPLEXITY HIGH PERFORMANCE DATA ACQUISITION CHIP USING 0.18 MICRON TECHNOLOGY

Data acquisition (DAQ) in the general sense is the process of collecting information from the real world. For engineers and scientists, this data is mostly numerical and is usually collected, stored and analysed using computers. However, most of the input signals cannot be read directly by digital computers. Because they are generally analog signals distinguished by continuous values, while computers can only recognise digital signals containing only the on/off levels. DAQ systems are therefore inevitably necessary, as they include the translation requirements from analog signals to digital data. For this reason, they have become significant in wide range of applications in modern science and technology [1]. The paper precents the disign of a 12-bit high-speed low-power Data Acquisition (DAQ) Chip. In this paper, the disigns of the building block components are aimed at high-accuracy along with high-speed and low power dissipation. A modifided flash Analog-to-Digital converter (ADC) was used instead of the traditional flash proposed DAQ chip operates at 1 GHz master clock frequency and achieves a sampling speed of 125 MS/s. It dissipates only 64.9 mW of power as compared to 97.2 mW when traditional flash ADC was used.